Michel Heily
97704f2621
core: debugger: Fix traces
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Former-commit-id: fbdaef86e2164ad1eeb5267041070958c024ceda
Former-commit-id: 643bcfe7ebccf77297d2371715490b3005e91d92
2021-06-09 02:01:42 +03:00
Michel Heily
28a57a874a
core: dma: Reduce logs
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Former-commit-id: 6db019b583e195fcb6aedb134cf54482a6c72428
Former-commit-id: 9294c305aafac1d55f18f1bd5d2fb5c62db509c5
2020-11-06 06:26:00 -08:00
Michel Heily
8afb443354
core: dma; Calculate address adjustment once
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Former-commit-id: 4f988e337a809e21fdec936d504dbfa399b6c496
Former-commit-id: e46f9a6791ff162cad0b5d11f33c035620637514
2020-10-18 08:33:37 -07:00
Michel Heily
fc7ad01cc0
Forgot to restore scheduler pointers when restoring savestate :)
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Former-commit-id: c6968e6767f0aa996a908a1444ce63bafd8b427d
Former-commit-id: ce636212835f50745c7edeb32e1fed925850b7c8
2020-10-18 08:32:44 -07:00
Michel Heily
44c9e2c875
core: dma: Count cycles passed in DMA transfers
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Former-commit-id: 751f2e42f9c5c19f2fcc901754950d1e3797303b
Former-commit-id: 30d31be99daec4324532d4663390945a55f641b1
2020-10-17 06:36:02 -07:00
Michel Heily
97101d7bc1
core: dma: Delay DMA by 3 cycles
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Former-commit-id: 06426b01a3e9e9084c97cd8f3a3de3b3c2b207e6
Former-commit-id: 2dee7bc2a2a3a3e69c7afa878f2d03208f330752
2020-10-17 06:36:02 -07:00
Michel Heily
529c9752c4
fix: Ignore top 4 bits of DMA addresses
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Former-commit-id: 3a5e691ca617803ef61f7a534c70d1cf04f36cb9
Former-commit-id: 289fad7340cbb18c51ecccd43e44682b37c78a1a
2020-10-03 21:58:32 +03:00
Michel Heily
554edd62b0
core: Properly set SharedInterruptFlags pointer for all interrupt generating devices when restoring state.
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Serde doesn't like Rc that much :(
Fixes #142
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Former-commit-id: 28366bbb36b3e93b574f397b103a483844fd8131
2020-09-27 15:44:17 +03:00
Michel Heily
879374a9b0
Refactor dir rustboyadvance-core -> core
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Former-commit-id: 748e222a36362eb5ac8909068c32f2d3f98ca536
2020-05-30 13:43:37 +03:00
