Commit graph

15 commits

Author SHA1 Message Date
Michel Heily
923032f8cf REPL UI changes
Former-commit-id: 6852b86541f967785dbffb6833fc2c11fa5dbef3
2019-07-04 01:37:47 +03:00
Michel Heily
3541779fbf Fix LR when changing cpu modes
Former-commit-id: 0ac911ee90758b9bffaafd459f1d9bca86d5064d
2019-07-04 01:37:05 +03:00
Michel Heily
4011911cca Pass around "Bus" instead of "SysBus"
Former-commit-id: c20dae7dd3ddcb3bd8f671a16fd67a241bd6c459
2019-07-03 01:22:36 +03:00
Michel Heily
6f81c236a6 Mega Commit #2 - Add some thumb decoding and disassembly
Former-commit-id: e3a89ac681a8d6f6f0bee85b32f64d181e11242f
2019-07-03 00:03:35 +03:00
Michel Heily
6b225d776d Implement all memory mappings. Reformat many files.
Former-commit-id: c0a62b610e62d2db2a4daf4aeef40068820daa52
2019-07-01 17:45:29 +03:00
Michel Heily
bd053354cb Implement LDR/STR (not tested) and add cycle counting
Former-commit-id: ec9e6bfc2a94291e47d41ff7d839007879d3d694
2019-06-30 16:59:37 +03:00
Michel Heily
967ccca8dd Mega commit - model CPU pipelining.
I except many bugs to arise..


Former-commit-id: bcc6ea57af803f783b0dd548b50956b3ccda2b1a
2019-06-29 22:23:12 +03:00
Michel Heily
d11620e65b cpu: Add SWI instruction
Also cleanup code, and add a test for swi decoding
2019-06-28 11:46:36 +03:00
Michel Heily
1a0725f1a3 cpu: Model exceptions 2019-06-27 15:13:38 +03:00
Michel Heily
6552329310 cpu: Kinda implement data processing instructions
When I say "Kinda", I mean that it is not tested well.
2019-06-27 13:16:00 +03:00
Michel Heily
5808c03fcd cpu: Model Program Status Register. 2019-06-27 13:15:46 +03:00
Michel Heily
e5d93f689f Work..
Refactor disassembler to a struct.
Implement more commands;
2019-06-27 13:15:34 +03:00
Michel Heily
22a915ec85 Add continue command 2019-06-27 13:15:34 +03:00
Michel Heily
9921f1c974 Add info and reset commands 2019-06-27 13:15:34 +03:00
Michel Heily
9330c53957 Start modeling CPU
Wrote a shallow skeleton of a CPU Core.
Finally made the disassembler a clap subcommand.
2019-06-27 13:15:19 +03:00