Michel Heily
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923032f8cf
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REPL UI changes
Former-commit-id: 6852b86541f967785dbffb6833fc2c11fa5dbef3
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2019-07-04 01:37:47 +03:00 |
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Michel Heily
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3541779fbf
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Fix LR when changing cpu modes
Former-commit-id: 0ac911ee90758b9bffaafd459f1d9bca86d5064d
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2019-07-04 01:37:05 +03:00 |
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Michel Heily
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4011911cca
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Pass around "Bus" instead of "SysBus"
Former-commit-id: c20dae7dd3ddcb3bd8f671a16fd67a241bd6c459
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2019-07-03 01:22:36 +03:00 |
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Michel Heily
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6f81c236a6
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Mega Commit #2 - Add some thumb decoding and disassembly
Former-commit-id: e3a89ac681a8d6f6f0bee85b32f64d181e11242f
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2019-07-03 00:03:35 +03:00 |
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Michel Heily
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6b225d776d
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Implement all memory mappings. Reformat many files.
Former-commit-id: c0a62b610e62d2db2a4daf4aeef40068820daa52
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2019-07-01 17:45:29 +03:00 |
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Michel Heily
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bd053354cb
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Implement LDR/STR (not tested) and add cycle counting
Former-commit-id: ec9e6bfc2a94291e47d41ff7d839007879d3d694
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2019-06-30 16:59:37 +03:00 |
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Michel Heily
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967ccca8dd
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Mega commit - model CPU pipelining.
I except many bugs to arise..
Former-commit-id: bcc6ea57af803f783b0dd548b50956b3ccda2b1a
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2019-06-29 22:23:12 +03:00 |
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Michel Heily
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d11620e65b
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cpu: Add SWI instruction
Also cleanup code, and add a test for swi decoding
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2019-06-28 11:46:36 +03:00 |
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Michel Heily
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1a0725f1a3
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cpu: Model exceptions
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2019-06-27 15:13:38 +03:00 |
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Michel Heily
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6552329310
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cpu: Kinda implement data processing instructions
When I say "Kinda", I mean that it is not tested well.
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2019-06-27 13:16:00 +03:00 |
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Michel Heily
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5808c03fcd
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cpu: Model Program Status Register.
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2019-06-27 13:15:46 +03:00 |
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Michel Heily
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e5d93f689f
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Work..
Refactor disassembler to a struct.
Implement more commands;
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2019-06-27 13:15:34 +03:00 |
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Michel Heily
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22a915ec85
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Add continue command
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2019-06-27 13:15:34 +03:00 |
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Michel Heily
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9921f1c974
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Add info and reset commands
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2019-06-27 13:15:34 +03:00 |
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Michel Heily
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9330c53957
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Start modeling CPU
Wrote a shallow skeleton of a CPU Core.
Finally made the disassembler a clap subcommand.
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2019-06-27 13:15:19 +03:00 |
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