Michel Heily
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d4b6952411
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Impl Thumb 19, fix warnings and rustfmt
Former-commit-id: 8690aa25b1aa343b344776716b6213596bd1459a
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2019-07-05 15:34:52 +03:00 |
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Michel Heily
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b82874809f
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Implement thumb format3 instruction and add a test for it.
Former-commit-id: 8cf6664027dc3d5dbeb6d2ca3d089820baac2709
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2019-07-03 01:26:48 +03:00 |
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Michel Heily
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6f81c236a6
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Mega Commit #2 - Add some thumb decoding and disassembly
Former-commit-id: e3a89ac681a8d6f6f0bee85b32f64d181e11242f
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2019-07-03 00:03:35 +03:00 |
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Michel Heily
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cbddeffd91
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arm: Implement MSR_REG and fix some prefetching errors
Former-commit-id: 177b8966159ed86472b0d4d031363df72d46807a
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2019-07-02 16:53:29 +03:00 |
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Michel Heily
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05fb40c17c
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debugger: Add Deref expression.
i.e:
r5 = *r6
r5 = *(u8*)r6
r5 = *(u16*)0x08000000
Former-commit-id: 962dade8e3c0b9f291115285137cf51b0abde266
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2019-07-02 13:36:52 +03:00 |
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Michel Heily
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6b225d776d
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Implement all memory mappings. Reformat many files.
Former-commit-id: c0a62b610e62d2db2a4daf4aeef40068820daa52
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2019-07-01 17:45:29 +03:00 |
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Michel Heily
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bd053354cb
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Implement LDR/STR (not tested) and add cycle counting
Former-commit-id: ec9e6bfc2a94291e47d41ff7d839007879d3d694
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2019-06-30 16:59:37 +03:00 |
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Michel Heily
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967ccca8dd
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Mega commit - model CPU pipelining.
I except many bugs to arise..
Former-commit-id: bcc6ea57af803f783b0dd548b50956b3ccda2b1a
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2019-06-29 22:23:12 +03:00 |
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Michel Heily
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d11620e65b
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cpu: Add SWI instruction
Also cleanup code, and add a test for swi decoding
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2019-06-28 11:46:36 +03:00 |
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Michel Heily
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1a0725f1a3
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cpu: Model exceptions
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2019-06-27 15:13:38 +03:00 |
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Michel Heily
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6552329310
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cpu: Kinda implement data processing instructions
When I say "Kinda", I mean that it is not tested well.
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2019-06-27 13:16:00 +03:00 |
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Michel Heily
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9330c53957
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Start modeling CPU
Wrote a shallow skeleton of a CPU Core.
Finally made the disassembler a clap subcommand.
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2019-06-27 13:15:19 +03:00 |
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Michel Heily
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addea1efa0
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Merge both packages
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2019-06-24 22:02:00 +03:00 |
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