4 commits

Author	SHA1	Message	Date
Michel Heily	be9499c76d	Move cycle counting to CPU Core ... This isn't accurate, I'm probably missing something but at least it'll make the instruction implementation more clean for now.. Former-commit-id: de24b15e1a51e1998207e5ea96fc8543f2553a26	2019-07-05 13:08:07 +03:00
Michel Heily	6f81c236a6	Mega Commit #2 - Add some thumb decoding and disassembly ... Former-commit-id: e3a89ac681a8d6f6f0bee85b32f64d181e11242f	2019-07-03 00:03:35 +03:00
Michel Heily	6b225d776d	Implement all memory mappings. Reformat many files. ... Former-commit-id: c0a62b610e62d2db2a4daf4aeef40068820daa52	2019-07-01 17:45:29 +03:00
Michel Heily	bd053354cb	Implement LDR/STR (not tested) and add cycle counting ... Former-commit-id: ec9e6bfc2a94291e47d41ff7d839007879d3d694	2019-06-30 16:59:37 +03:00