Michel Heily
702a08e30c
Add many thumb instructions..
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TODO add more tests for all the instructions I've got implemented so
far.
Also, I need to rewrite the whole "sysbus" module again because it's
crap and I keep refactoring it as I go.
I've added the "Dummy" because the bios for some reason tries to memzero
an unmapped region on the work ram (the thumb loop that ends at 0x126)
Former-commit-id: 67befd0935ee10df9ac8ceeaebd14f69767a7f16
2019-07-04 01:56:50 +03:00
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28743702a1
Update waitstates for 256k work ram
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Former-commit-id: f5680c90e4ab4a9b29899cd5e0fe316d8227fc24
2019-07-03 11:30:00 +03:00
Michel Heily
58e1230e7a
Model the cartidge.
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Former-commit-id: b51d2928631bfc438b9f1b15fafcaa9d90008179
2019-07-03 01:40:08 +03:00
Michel Heily
b82874809f
Implement thumb format3 instruction and add a test for it.
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Former-commit-id: 8cf6664027dc3d5dbeb6d2ca3d089820baac2709
2019-07-03 01:26:48 +03:00
Michel Heily
4011911cca
Pass around "Bus" instead of "SysBus"
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Former-commit-id: c20dae7dd3ddcb3bd8f671a16fd67a241bd6c459
2019-07-03 01:22:36 +03:00
Michel Heily
6f81c236a6
Mega Commit #2 - Add some thumb decoding and disassembly
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Former-commit-id: e3a89ac681a8d6f6f0bee85b32f64d181e11242f
2019-07-03 00:03:35 +03:00
Michel Heily
6b225d776d
Implement all memory mappings. Reformat many files.
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Former-commit-id: c0a62b610e62d2db2a4daf4aeef40068820daa52
2019-07-01 17:45:29 +03:00
Michel Heily
bd053354cb
Implement LDR/STR (not tested) and add cycle counting
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Former-commit-id: ec9e6bfc2a94291e47d41ff7d839007879d3d694
2019-06-30 16:59:37 +03:00
Michel Heily
e5d93f689f
Work..
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Refactor disassembler to a struct.
Implement more commands;
2019-06-27 13:15:34 +03:00
Michel Heily
9330c53957
Start modeling CPU
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Wrote a shallow skeleton of a CPU Core.
Finally made the disassembler a clap subcommand.
2019-06-27 13:15:19 +03:00
