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Author SHA1 Message Date
Michel Heily bfee970592 Update Cargo.lock 
Former-commit-id: 91eeaeccafc9eee20aee6b103176b4ee9d42c742
 2019-11-09 19:44:55 +02:00
Michel Heily f898de8ddc Update launch.json for cppvsdbg 
Former-commit-id: 6fc91daa80dd77bcefb82880217b4b1d85bfcdb5
 2019-11-09 19:44:55 +02:00
Michel Heily c78a111ad4 Implement DMA, WIP 
I have fought very hard against the rust ownership model,
In the end for DMA to play nice with my code, I had to resort to use
unsafe code for now..

The DMA implementation itself is not accurate to say the least, but will
have to do for now.

Tonc's dma_demo.gba plays but with a visual glitch.


Former-commit-id: 3b9cdcb2d09c78701290f2c48b77f9f3487e85c9
 2019-11-09 19:44:55 +02:00
Michel Heily 3a1d5c10ce Fix many bugs, refactor many things.. 
Passing: Armwrestler, cpu_test by Dead_Body

Former-commit-id: 80d815d110c5341515dd01c476a0d7e25ecb66a8
 2019-11-09 01:06:24 +02:00
Michel Heily 2bd8b56bc6 Fix that DAMN bug. 
Long story short, I've been hunting this bug for a while now.
While passing armwresteler tests, I still had an emulation bug which
causeed libgcc's iprintf to produce bugged strings.

In order to find it, I've used https://github.com/fleroviux/NanoboyAdvance/
And patched it to produce a formatted log of every step of the execution
of iprintf:
{OPCODE} {PC} {R0} {R1} ... {R14} {FLAGS}
Did the same on my emulator and searched for differences.

Found out the a "CMP r3, #0x0" instruction turned off the carry flag
when it shouldn't. Found this sad function, the check I'm using for
carry flag is meaningless when done on signed integers. :sigh:


Former-commit-id: 871d2581921796dae9bf4f5fdaa45c6ad46aebec
 2019-11-06 00:49:59 +02:00
Michel Heily 7cc1a50d12 Support zip files and add --no-framerate-limit 
Former-commit-id: 62a7122fb0b3e832eeb3cbf347a0966e4cd32d50
 2019-09-11 21:26:40 +03:00
Michel Heily fa211fa77e Fix thumb NEG instruction. Finally pass armwrestler! 
This one took me quite a bit. :/


Former-commit-id: f08537dda5a62076c3faff31a898c0a585102526
 2019-09-10 01:01:49 +03:00
Michel Heily 441482516e Get rid of timer.rs spam 
Former-commit-id: 2d2ce31ad77840e4a8685257a77f824da21992ba
 2019-09-09 20:07:45 +03:00
Michel Heily 9ebb0d3d2d Fix OBJ priorities (tonc prio_demo.gba works) 
Former-commit-id: a55b3be7688ef7e1446a54c38fc5ddb5034cb4b9
 2019-08-31 14:13:21 +02:00
Michel Heily ba9b4662d4 Fix SBC and RSC instructions 
Needed to add 1-C and not substract 1-C


Former-commit-id: 339201a2cd41d777d3b3204995e698182032c80d
 2019-08-31 14:10:05 +02:00
Michel Heily eab08992b9 Add normal sprite rendering support. 
Former-commit-id: 04c3d7ec3051ce4c5aeacb552688c0217b3b3d3b
 2019-08-27 23:15:22 +03:00
Michel Heily 8abebbe844 Implement Window special effect (win_demo.gba works, excpet the sprite) 
Former-commit-id: 511d04045bbb678ceec39e34c483f04db154997b
 2019-08-24 00:36:48 +03:00
Michel Heily 1d2d950729 Fix IoRegs::write_8 
Former-commit-id: 9877e7f42fefafb71dd319287e01d55926d4d12c
 2019-08-24 00:33:01 +03:00
Michel Heily f40ee148ea Add sdl2 key mappings 
Former-commit-id: 9b3aa941ffca9a679d9ce70ca43d6396d4dfe5ff
 2019-08-23 22:47:12 +03:00
Michel Heily 4a72a1035f Fix Rgb15::is_transparent bug 
Former-commit-id: f12729b993ec9bef94a58a4d48982c7d3939c45b
 2019-08-17 21:27:36 +03:00
Michel Heily 639993edd7 Add blending and mosaic SFX, and cleanup code. 
Former-commit-id: b9f0ccaf1820da61f49ebeb2af5beff5cccd722f
 2019-08-13 22:15:36 +03:00
Michel Heily c4b24fde02 Refactor GPU registers wrappers to a separate module 
Former-commit-id: 3e7c6326232cd761674061ceed758a56412da17f
 2019-08-11 22:35:32 +03:00
Michel Heily 52ef793759 Move gpu module to a separate folder, to allow for later cleanup. 
Also, get rid of "render" command


Former-commit-id: 7dd004f3ff8f55686665adead497ebae4f873379
 2019-08-11 22:28:52 +03:00
Michel Heily edf2efcce5 Fix panic if debugger histfile does not exist 
Former-commit-id: a355a783b4d513dd3c65ef41de6a7604853a7b0f
 2019-08-11 21:50:44 +03:00
Michel Heily 9064ae9cf8 Fix bug in IoRegs::write_32 
Former-commit-id: a2c5b57a0e7da2fa0f080d70acd77b8643bc4742
 2019-08-11 21:50:44 +03:00
Michel Heily 3f6a52cae6 Add sdl2 backend 
Currently has bad performance


Former-commit-id: 384ef6b5cd7b1e1baeb6adfbc0b299b0d07d7a5d
 2019-08-10 18:14:59 +03:00
Michel Heily acd0e4f338 cpu: Refactor instructions to use explicit cycle counting. 
The way cycles were counted up untill now was not accurate enough,
I've avoided doing so because the instruction implementation looks
bloated this way, but I've had problems with cycle accuracy with tonc's
timer demo.

This is not entirely correct though, and I'm 100% sure there are some
mistakes, but works good enough for now.


Former-commit-id: 748faaf99fe2f42925c0a2110192c6a01e5d27d4
 2019-08-08 20:05:09 +03:00
Michel Heily d86cc87c79 Add WAITCNT, and refactor cycle calculation 
Former-commit-id: e1ee5c9ce1f1db549fddd80907467da51e63b676
 2019-08-07 09:50:33 +03:00
Michel Heily fe071bf1ec Fix timer bugs 
Former-commit-id: 9839368895dca306b66a095ab0b9386c77bd2c12
 2019-08-07 09:45:10 +03:00
Michel Heily c72bbb96fd [WIP] Timers 
Seems to work, but the cycle's are not accurate so they run slowly


Former-commit-id: a0b80acb4b68ed64caa535a0ec9f75a081d3aed4
 2019-08-05 09:53:41 +03:00
Michel Heily c7dd713605 The big ioregs refactoring. 
This commit refactors the ioregs:
* Use bitfield crate to implement the GPU ioregs.
* IoRegs are stored in their own variables bindings (i.e, Gpu related ioregs are now fields of the Gpu struct)
  - This optimize performance quiet alot from my testings - since every scanline was accessing deseralizing ioregs from sysbus. (Getting constant 59fps now)
* For now, comment out DMA model

Also, cleaned the code up to eliminate rustc warnings.


Former-commit-id: 9077695c446ebd1a71783acfdd9819245aa02d7a
 2019-08-03 00:24:15 +03:00
Michel Heily 9f0df9af06 optimization: Optimize VRAM accesses from within the gpu. 
Not going through the memory mapping anymore.

Also, this commit wraps the gpu pixeldata with a struct


Former-commit-id: d7b706d9de61bac7909e10d6bbe092968e6acc9f
 2019-08-02 18:04:35 +03:00
Michel Heily eb2a1a02fe Implement background scrolling! 
tonc's brin_demo.gba now works as intended :)


Former-commit-id: 596c063c5968534f42e42f52203c85262b9c6fa2
 2019-07-31 00:52:46 +03:00
Michel Heily f862209911 Support axis flip for tiles 
Former-commit-id: daefb380ab2dfcee600297690dcc0c7c1a37f911
 2019-07-29 09:46:12 +03:00
Michel Heily 90edebbe82 Align to halfword for thumb branch long instructions 
Former-commit-id: f75e4baf003dcb7c535db3692383cc95575dfd81
 2019-07-29 01:55:16 +03:00
Michel Heily e962150aaf Start working on Interrupts. 
it kinda works now, but needs testing.


Former-commit-id: 8510314cce248a737d492d935cf5b48f86d920ed
 2019-07-29 01:28:22 +03:00
Michel Heily 66a484e3ae Fix mode0 calculation of tile map entries. 
tonc's hello.gba demo now works correctly :)


Former-commit-id: ead3a01e810f69503abbe8bddd0853433862549b
 2019-07-27 23:28:00 +03:00
Michel Heily f39095a03b Fix thumb conditional branch offset 
Former-commit-id: b42f233b7f2ca5d427b0e36860a305f7e1a26a1d
 2019-07-27 21:30:27 +03:00
Michel Heily df48f307f0 armwrestler-fix: Fix post indexed LDR_STR when rd==rn 
Former-commit-id: b886c969c2d570fbb831eeeddc0f65ad575cfccb
 2019-07-27 21:28:43 +03:00
Michel Heily 477b4f45fd Fix thumb MUL not setting the flags 
Former-commit-id: b43e35a7fa2894fcc5cef7eeae9d74123e40219b
 2019-07-27 20:25:59 +03:00
Michel Heily 44426b5f0e Impl arm SWP 
Also ran some rustfmt


Former-commit-id: 30480e79d7f2926d5a5f15db20427179a672a78c
 2019-07-27 20:20:58 +03:00
Michel Heily e06c77b6fd armwrestler-fix: Fix MULL_MLAL instructions 
Also fix disassembly for MULL_MLAL


Former-commit-id: f535b2db7edb5d056160699436dbeb0c15e61388
 2019-07-27 18:57:20 +03:00
Michel Heily 7429236471 Fix mistake in UMLAL 
Former-commit-id: 6fe9bdf5471b71b58dcf9ee9ffa03c41b24e6301
 2019-07-26 17:55:50 +03:00
Michel Heily 1b5626a1a7 armwrestler-fix: Refactor barrel shifter and fix ALU carry flag, hopefully for good. 
Passing most of armwrestler ALU tests (still have bugs in UMULL and
SMULL)


Former-commit-id: 3c57ca9b5360b5c9bba74b00a5bede5a8cc496af
 2019-07-26 17:55:50 +03:00
Michel Heily 24483456ed armwrestler-fix: Fix writeback for LDR where rd==rn 
Instead of returning an Err, the writeback should just be disabled.


Former-commit-id: 91636a4eeaf76d0dbd11d250202671fcf8aaa4e6
 2019-07-22 20:33:31 +03:00
Michel Heily 009e46f6d5 armwrestler-fix: Properly handle misaligned addresses LDR/LDRH/LDRSH 
Former-commit-id: 742a7c2b8413fa9d45df1575a0b14b8d1ab697c4
 2019-07-22 20:25:40 +03:00
Michel Heily 2a66e525b1 Fix thumb disassembly of LDMIA/STMIA 
Former-commit-id: b04b07f181fff82869503671dd0f500a6c3e5fb1
 2019-07-22 09:31:35 +03:00
Michel Heily 2fb6f3c884 Implement (psr / usr bank) transfers for LDM_STM 
Former-commit-id: 140e6a6c75f65f08f645b1a0ff2ca7c065438ce4
 2019-07-22 09:21:49 +03:00
Michel Heily 0b5902c52e Implement special MRS 
Former-commit-id: 1af358887ef71344987f72d65612095c72565f43
 2019-07-22 09:21:45 +03:00
Michel Heily c0d437b1a1 Fix exceptions and dataprocess mode change 
Former-commit-id: 5892131496904b621398212b9dfc077242fa9557
 2019-07-22 01:16:48 +03:00
Michel Heily 7501adfd12 Implement thumb17 (Swi) 
Former-commit-id: 62d7e14e9b84e74d9236e1f0a5e961ae805f861c
 2019-07-22 01:15:58 +03:00
Michel Heily eea26d2393 thumb: Change ordering when decoding thumb instruction. 
This fixes a bug where "swi" instructions are decoded as conditional
branches.

The order really matters here, because Swi instructions are actually
conditional branch with illegal condition code.


Former-commit-id: 0024a8b53386a510dd321c157391c99a2af29223
 2019-07-22 00:25:26 +03:00
Michel Heily 387e26fad9 Add support for BGMode3 (tonc first.gba example now working) 
Former-commit-id: 52ac773ee2c3542ff3b046c3ea33fde02e804492
 2019-07-22 00:09:44 +03:00
Michel Heily 7e9c0e31da Add minifb backend - Armwrestler now plays ! 
Former-commit-id: d72ea9139e04624322cf3bc4a8ab330f6bb133a4
 2019-07-20 23:02:18 +03:00
Michel Heily 61e1f055f1 Model the keypad 
Former-commit-id: 4f38fa754e3ee809a7386351297decb2d7f1451f
 2019-07-20 22:58:29 +03:00