Michel Heily
53115a9a58
Refactor core functionality into a separate module
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Former-commit-id: 5d55b9eb0b63ed7c61465b4e814782165caa5002
2019-07-20 16:46:00 +03:00
Michel Heily
7119ba2451
Cpu: Rewrite pipeline code.
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Pipeline code was unreadable up until now, this also fixes a bug:
* Some roms have illegal instructions right after branch instructions, and
the cpu would error trying to decode them because of pipelining.
Former-commit-id: e3201c7b0d2adfc772231a3e2d5909f43c17b50f
2019-07-20 16:03:37 +03:00
Michel Heily
0500d33cb7
Refactor bus interface
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Former-commit-id: f325cda23f5e9946b367456d82ba71bb92bdd46e
2019-07-15 07:30:52 +03:00
Michel Heily
fb5229705b
Refactor and fix arm condition check
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Former-commit-id: 132c14fc56a21426263971e2d544ff10f072fea1
2019-07-13 23:32:43 +03:00
Michel Heily
863838a4a4
Force R15 alignment via cpu.set_reg
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I've encounted many bugs with instructions that write PC but don't align
it.
Former-commit-id: b6a234564729f83c0b5e8adfa293227299aad4ac
2019-07-08 00:57:18 +03:00
Michel Heily
c2685c14d7
Impl more thumb, Fix more things, the usual
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Former-commit-id: 02f1898bfd8dd50519f103bb367e358fc55c46e7
2019-07-06 23:38:08 +03:00
Michel Heily
36dba78c55
More fixes
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Former-commit-id: 897cbc0fb9c12469606c48ee8a02d35bf82c2ae5
2019-07-06 18:48:22 +03:00
Michel Heily
3cc84b1b03
Model many things
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Former-commit-id: b87fa2b16b395f497cf217ea043e68404ab2f65e
2019-07-06 15:54:07 +03:00
Michel Heily
058760d7e4
Impl thumb Format4
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Former-commit-id: 7b8705ee7b76bbeb5b2a21e830d16db06ce8d63c
2019-07-05 13:58:26 +03:00
Michel Heily
be9499c76d
Move cycle counting to CPU Core
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This isn't accurate, I'm probably missing something but at least it'll
make the instruction implementation more clean for now..
Former-commit-id: de24b15e1a51e1998207e5ea96fc8543f2553a26
2019-07-05 13:08:07 +03:00
Michel Heily
e66a8a9a3b
Fix LR again :(
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Former-commit-id: 820315154ae58dcc29c4a8921094598f149b0255
2019-07-05 03:27:23 +03:00
Michel Heily
923032f8cf
REPL UI changes
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Former-commit-id: 6852b86541f967785dbffb6833fc2c11fa5dbef3
2019-07-04 01:37:47 +03:00
Michel Heily
3541779fbf
Fix LR when changing cpu modes
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Former-commit-id: 0ac911ee90758b9bffaafd459f1d9bca86d5064d
2019-07-04 01:37:05 +03:00
Michel Heily
4011911cca
Pass around "Bus" instead of "SysBus"
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Former-commit-id: c20dae7dd3ddcb3bd8f671a16fd67a241bd6c459
2019-07-03 01:22:36 +03:00
Michel Heily
6f81c236a6
Mega Commit #2 - Add some thumb decoding and disassembly
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Former-commit-id: e3a89ac681a8d6f6f0bee85b32f64d181e11242f
2019-07-03 00:03:35 +03:00
Michel Heily
6b225d776d
Implement all memory mappings. Reformat many files.
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Former-commit-id: c0a62b610e62d2db2a4daf4aeef40068820daa52
2019-07-01 17:45:29 +03:00
Michel Heily
bd053354cb
Implement LDR/STR (not tested) and add cycle counting
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Former-commit-id: ec9e6bfc2a94291e47d41ff7d839007879d3d694
2019-06-30 16:59:37 +03:00
Michel Heily
967ccca8dd
Mega commit - model CPU pipelining.
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I except many bugs to arise..
Former-commit-id: bcc6ea57af803f783b0dd548b50956b3ccda2b1a
2019-06-29 22:23:12 +03:00
Michel Heily
d11620e65b
cpu: Add SWI instruction
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Also cleanup code, and add a test for swi decoding
2019-06-28 11:46:36 +03:00
Michel Heily
1a0725f1a3
cpu: Model exceptions
2019-06-27 15:13:38 +03:00
Michel Heily
6552329310
cpu: Kinda implement data processing instructions
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When I say "Kinda", I mean that it is not tested well.
2019-06-27 13:16:00 +03:00
Michel Heily
5808c03fcd
cpu: Model Program Status Register.
2019-06-27 13:15:46 +03:00
Michel Heily
e5d93f689f
Work..
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Refactor disassembler to a struct.
Implement more commands;
2019-06-27 13:15:34 +03:00
Michel Heily
22a915ec85
Add continue command
2019-06-27 13:15:34 +03:00
Michel Heily
9921f1c974
Add info and reset commands
2019-06-27 13:15:34 +03:00
Michel Heily
9330c53957
Start modeling CPU
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Wrote a shallow skeleton of a CPU Core.
Finally made the disassembler a clap subcommand.
2019-06-27 13:15:19 +03:00
