Michel Heily
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967ccca8dd
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Mega commit - model CPU pipelining.
I except many bugs to arise..
Former-commit-id: bcc6ea57af803f783b0dd548b50956b3ccda2b1a
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2019-06-29 22:23:12 +03:00 |
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Michel Heily
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4c75970512
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debugger: Detect error
Former-commit-id: 1ea605eeab1a7b8e6645fe11d7b32c4c7dff0750
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2019-06-29 01:48:29 +03:00 |
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Michel Heily
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2238c7a72f
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Add demo gif to README.md
Former-commit-id: 05ec55725c04cd4d4ca08471ea88b1b6b1b11e08
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2019-06-28 15:32:21 +03:00 |
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Michel Heily
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c90448075f
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debugger: Fix breakpoint hit message
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2019-06-28 15:07:29 +03:00 |
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Michel Heily
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64e0a02754
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Add .vscode configuration for easy debugging
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2019-06-28 15:05:18 +03:00 |
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Michel Heily
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3429b67c41
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Fix test_decode_branch_backwards failing
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2019-06-28 13:09:30 +03:00 |
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Michel Heily
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5245f0780c
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Update README.md
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2019-06-28 13:05:48 +03:00 |
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Michel Heily
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bd7fd472cf
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arm: Add tests for ldr/str
And also test disassembling while at it..
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2019-06-28 12:36:19 +03:00 |
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Michel Heily
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7898bf61f3
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arm: Fix bug when calculating 24bit branch offsets, and add a test for
it.
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2019-06-28 12:01:49 +03:00 |
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Michel Heily
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d11620e65b
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cpu: Add SWI instruction
Also cleanup code, and add a test for swi decoding
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2019-06-28 11:46:36 +03:00 |
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Michel Heily
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1a0725f1a3
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cpu: Model exceptions
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2019-06-27 15:13:38 +03:00 |
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Michel Heily
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fc6410b510
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debugger: Make prompt bold
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2019-06-27 15:04:15 +03:00 |
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Michel Heily
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1d766e95de
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cpu: Fix bug in psr mode bits
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2019-06-27 15:03:44 +03:00 |
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Michel Heily
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948e0ccc25
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Fix typo in .travis.yml
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2019-06-27 13:16:00 +03:00 |
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Michel Heily
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b9d1d38c2d
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debugger: Few improvements
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2019-06-27 13:16:00 +03:00 |
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Michel Heily
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6552329310
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cpu: Kinda implement data processing instructions
When I say "Kinda", I mean that it is not tested well.
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2019-06-27 13:16:00 +03:00 |
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Michel Heily
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5808c03fcd
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cpu: Model Program Status Register.
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2019-06-27 13:15:46 +03:00 |
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Michel Heily
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8a057ba159
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debugger: Remember last command
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2019-06-27 13:15:46 +03:00 |
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Michel Heily
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587ec3fc91
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debugger: Add history to repl
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2019-06-27 13:15:46 +03:00 |
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Michel Heily
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f45a856835
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Support assignment expressions for registers!
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2019-06-27 13:15:46 +03:00 |
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Michel Heily
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f1f33d8586
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Improve debugger repl parsing.
Add assignment expressions, add tests, and cleanup code.
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2019-06-27 13:15:46 +03:00 |
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Michel Heily
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a70b92d5a4
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Rename project
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2019-06-27 13:15:46 +03:00 |
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Michel Heily
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fc400ace5f
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Improve debug repl parsing :)
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2019-06-27 13:15:46 +03:00 |
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Michel Heily
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e5d93f689f
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Work..
Refactor disassembler to a struct.
Implement more commands;
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2019-06-27 13:15:34 +03:00 |
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Michel Heily
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22a915ec85
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Add continue command
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2019-06-27 13:15:34 +03:00 |
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Michel Heily
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9921f1c974
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Add info and reset commands
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2019-06-27 13:15:34 +03:00 |
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Michel Heily
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fc28d89097
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Implement a few debugger commands
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2019-06-27 13:15:34 +03:00 |
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Michel Heily
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107e34aca1
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Start debugger repl
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2019-06-27 13:15:34 +03:00 |
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Michel Heily
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9330c53957
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Start modeling CPU
Wrote a shallow skeleton of a CPU Core.
Finally made the disassembler a clap subcommand.
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2019-06-27 13:15:19 +03:00 |
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Michel Heily
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addea1efa0
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Merge both packages
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2019-06-24 22:02:00 +03:00 |
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Michel Heily
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094cbb5f29
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Refactor disassembler binary into arm7tdmi package
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2019-06-24 21:45:25 +03:00 |
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Michel Heily
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5a5efae4c0
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Refactor disassembler => disass
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2019-06-24 20:53:56 +03:00 |
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Michel Heily
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dffb739d47
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Finish disassembler for now
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2019-06-24 20:20:08 +03:00 |
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Michel Heily
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377f350e12
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Start arm disassembler
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2019-06-24 16:36:20 +03:00 |
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Michel Heily
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f18ec05c17
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Create .travis.yml
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2019-06-24 16:36:20 +03:00 |
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MishMish
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4a67ecd1bc
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Create LICENSE
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2019-06-24 16:36:20 +03:00 |
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Michel Heily
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8324c1ed50
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Initial commit
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2019-06-24 16:36:20 +03:00 |
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