Commit graph

14 commits

Author SHA1 Message Date
Michel Heily
967ccca8dd Mega commit - model CPU pipelining.
I except many bugs to arise..


Former-commit-id: bcc6ea57af803f783b0dd548b50956b3ccda2b1a
2019-06-29 22:23:12 +03:00
Michel Heily
3429b67c41 Fix test_decode_branch_backwards failing 2019-06-28 13:09:30 +03:00
Michel Heily
bd7fd472cf arm: Add tests for ldr/str
And also test disassembling while at it..
2019-06-28 12:36:19 +03:00
Michel Heily
7898bf61f3 arm: Fix bug when calculating 24bit branch offsets, and add a test for
it.
2019-06-28 12:01:49 +03:00
Michel Heily
d11620e65b cpu: Add SWI instruction
Also cleanup code, and add a test for swi decoding
2019-06-28 11:46:36 +03:00
Michel Heily
1a0725f1a3 cpu: Model exceptions 2019-06-27 15:13:38 +03:00
Michel Heily
1d766e95de cpu: Fix bug in psr mode bits 2019-06-27 15:03:44 +03:00
Michel Heily
6552329310 cpu: Kinda implement data processing instructions
When I say "Kinda", I mean that it is not tested well.
2019-06-27 13:16:00 +03:00
Michel Heily
5808c03fcd cpu: Model Program Status Register. 2019-06-27 13:15:46 +03:00
Michel Heily
e5d93f689f Work..
Refactor disassembler to a struct.
Implement more commands;
2019-06-27 13:15:34 +03:00
Michel Heily
22a915ec85 Add continue command 2019-06-27 13:15:34 +03:00
Michel Heily
9921f1c974 Add info and reset commands 2019-06-27 13:15:34 +03:00
Michel Heily
9330c53957 Start modeling CPU
Wrote a shallow skeleton of a CPU Core.
Finally made the disassembler a clap subcommand.
2019-06-27 13:15:19 +03:00
Michel Heily
addea1efa0 Merge both packages 2019-06-24 22:02:00 +03:00