Michel Heily
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967ccca8dd
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Mega commit - model CPU pipelining.
I except many bugs to arise..
Former-commit-id: bcc6ea57af803f783b0dd548b50956b3ccda2b1a
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2019-06-29 22:23:12 +03:00 |
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Michel Heily
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3429b67c41
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Fix test_decode_branch_backwards failing
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2019-06-28 13:09:30 +03:00 |
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Michel Heily
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bd7fd472cf
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arm: Add tests for ldr/str
And also test disassembling while at it..
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2019-06-28 12:36:19 +03:00 |
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Michel Heily
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7898bf61f3
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arm: Fix bug when calculating 24bit branch offsets, and add a test for
it.
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2019-06-28 12:01:49 +03:00 |
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Michel Heily
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d11620e65b
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cpu: Add SWI instruction
Also cleanup code, and add a test for swi decoding
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2019-06-28 11:46:36 +03:00 |
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Michel Heily
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1a0725f1a3
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cpu: Model exceptions
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2019-06-27 15:13:38 +03:00 |
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Michel Heily
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1d766e95de
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cpu: Fix bug in psr mode bits
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2019-06-27 15:03:44 +03:00 |
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Michel Heily
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6552329310
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cpu: Kinda implement data processing instructions
When I say "Kinda", I mean that it is not tested well.
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2019-06-27 13:16:00 +03:00 |
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Michel Heily
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5808c03fcd
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cpu: Model Program Status Register.
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2019-06-27 13:15:46 +03:00 |
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Michel Heily
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e5d93f689f
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Work..
Refactor disassembler to a struct.
Implement more commands;
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2019-06-27 13:15:34 +03:00 |
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Michel Heily
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22a915ec85
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Add continue command
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2019-06-27 13:15:34 +03:00 |
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Michel Heily
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9921f1c974
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Add info and reset commands
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2019-06-27 13:15:34 +03:00 |
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Michel Heily
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9330c53957
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Start modeling CPU
Wrote a shallow skeleton of a CPU Core.
Finally made the disassembler a clap subcommand.
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2019-06-27 13:15:19 +03:00 |
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Michel Heily
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addea1efa0
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Merge both packages
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2019-06-24 22:02:00 +03:00 |
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