Commit graph

431 commits

Author SHA1 Message Date
Michel Heily 5245f0780c Update README.md 2019-06-28 13:05:48 +03:00
Michel Heily bd7fd472cf arm: Add tests for ldr/str
And also test disassembling while at it..
2019-06-28 12:36:19 +03:00
Michel Heily 7898bf61f3 arm: Fix bug when calculating 24bit branch offsets, and add a test for
it.
2019-06-28 12:01:49 +03:00
Michel Heily d11620e65b cpu: Add SWI instruction
Also cleanup code, and add a test for swi decoding
2019-06-28 11:46:36 +03:00
Michel Heily 1a0725f1a3 cpu: Model exceptions 2019-06-27 15:13:38 +03:00
Michel Heily fc6410b510 debugger: Make prompt bold 2019-06-27 15:04:15 +03:00
Michel Heily 1d766e95de cpu: Fix bug in psr mode bits 2019-06-27 15:03:44 +03:00
Michel Heily 948e0ccc25 Fix typo in .travis.yml 2019-06-27 13:16:00 +03:00
Michel Heily b9d1d38c2d debugger: Few improvements 2019-06-27 13:16:00 +03:00
Michel Heily 6552329310 cpu: Kinda implement data processing instructions
When I say "Kinda", I mean that it is not tested well.
2019-06-27 13:16:00 +03:00
Michel Heily 5808c03fcd cpu: Model Program Status Register. 2019-06-27 13:15:46 +03:00
Michel Heily 8a057ba159 debugger: Remember last command 2019-06-27 13:15:46 +03:00
Michel Heily 587ec3fc91 debugger: Add history to repl 2019-06-27 13:15:46 +03:00
Michel Heily f45a856835 Support assignment expressions for registers! 2019-06-27 13:15:46 +03:00
Michel Heily f1f33d8586 Improve debugger repl parsing.
Add assignment expressions, add tests, and cleanup code.
2019-06-27 13:15:46 +03:00
Michel Heily a70b92d5a4 Rename project 2019-06-27 13:15:46 +03:00
Michel Heily fc400ace5f Improve debug repl parsing :) 2019-06-27 13:15:46 +03:00
Michel Heily e5d93f689f Work..
Refactor disassembler to a struct.
Implement more commands;
2019-06-27 13:15:34 +03:00
Michel Heily 22a915ec85 Add continue command 2019-06-27 13:15:34 +03:00
Michel Heily 9921f1c974 Add info and reset commands 2019-06-27 13:15:34 +03:00
Michel Heily fc28d89097 Implement a few debugger commands 2019-06-27 13:15:34 +03:00
Michel Heily 107e34aca1 Start debugger repl 2019-06-27 13:15:34 +03:00
Michel Heily 9330c53957 Start modeling CPU
Wrote a shallow skeleton of a CPU Core.
Finally made the disassembler a clap subcommand.
2019-06-27 13:15:19 +03:00
Michel Heily addea1efa0 Merge both packages 2019-06-24 22:02:00 +03:00
Michel Heily 094cbb5f29 Refactor disassembler binary into arm7tdmi package 2019-06-24 21:45:25 +03:00
Michel Heily 5a5efae4c0 Refactor disassembler => disass 2019-06-24 20:53:56 +03:00
Michel Heily dffb739d47 Finish disassembler for now 2019-06-24 20:20:08 +03:00
Michel Heily 377f350e12 Start arm disassembler 2019-06-24 16:36:20 +03:00
Michel Heily f18ec05c17 Create .travis.yml 2019-06-24 16:36:20 +03:00
MishMish 4a67ecd1bc Create LICENSE 2019-06-24 16:36:20 +03:00
Michel Heily 8324c1ed50 Initial commit 2019-06-24 16:36:20 +03:00