Michel Heily
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70179984d0
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cpu: arm: Fix alu_add_update_carry function
Woopsie
Former-commit-id: 2da74e4bfd4b59a2885519a99f4b2c3d83031ee2
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2019-07-01 19:25:42 +03:00 |
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Michel Heily
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2081b70ee2
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cpu: arm: Fix R14 for branch with link instruction
Former-commit-id: bc927d86e5a170b0e4568b4ceeb7832d23ad309c
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2019-07-01 19:24:52 +03:00 |
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Michel Heily
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ea8c4f2a60
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Refactor ArmInstructionFormat => ArmFormat
Former-commit-id: 0ba6e1e6efedad55b2716b3f2ab5a2a629dd18a5
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2019-07-01 17:51:07 +03:00 |
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Michel Heily
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6b225d776d
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Implement all memory mappings. Reformat many files.
Former-commit-id: c0a62b610e62d2db2a4daf4aeef40068820daa52
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2019-07-01 17:45:29 +03:00 |
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Michel Heily
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bd053354cb
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Implement LDR/STR (not tested) and add cycle counting
Former-commit-id: ec9e6bfc2a94291e47d41ff7d839007879d3d694
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2019-06-30 16:59:37 +03:00 |
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Michel Heily
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967ccca8dd
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Mega commit - model CPU pipelining.
I except many bugs to arise..
Former-commit-id: bcc6ea57af803f783b0dd548b50956b3ccda2b1a
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2019-06-29 22:23:12 +03:00 |
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Michel Heily
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bd7fd472cf
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arm: Add tests for ldr/str
And also test disassembling while at it..
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2019-06-28 12:36:19 +03:00 |
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Michel Heily
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d11620e65b
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cpu: Add SWI instruction
Also cleanup code, and add a test for swi decoding
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2019-06-28 11:46:36 +03:00 |
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Michel Heily
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1a0725f1a3
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cpu: Model exceptions
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2019-06-27 15:13:38 +03:00 |
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Michel Heily
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6552329310
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cpu: Kinda implement data processing instructions
When I say "Kinda", I mean that it is not tested well.
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2019-06-27 13:16:00 +03:00 |
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Michel Heily
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e5d93f689f
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Work..
Refactor disassembler to a struct.
Implement more commands;
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2019-06-27 13:15:34 +03:00 |
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Michel Heily
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22a915ec85
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Add continue command
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2019-06-27 13:15:34 +03:00 |
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