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Author SHA1 Message Date
Michel Heily 6c0df33597 Finally got the barrel shifter right? 
The barrel shifter sure has lots of edge cases, need to implement tests ASAP


Former-commit-id: 989fc4477f610603154404d0ed4335619ebd6345
 2019-07-09 00:33:53 +03:00
Michel Heily 2817db4e1c alu: Fix carry detection for subtraction 
Former-commit-id: c9d8612f72ce4a002ea33446209bd7e6da0eb5aa
 2019-07-09 00:33:53 +03:00
Michel Heily 1bacb927af Fix ROR with amount > 32 
Former-commit-id: 8f88de3c55c0e452266c40944ff920175b83627e
 2019-07-08 21:03:47 +03:00
Michel Heily 9421281381 Fix THUMB 1 
I didn't send this through the ALU :/


Former-commit-id: 40b4d23dcd769496e9dcd47bbf8d472b91e6a7bf
 2019-07-08 20:58:22 +03:00
Michel Heily f7b2b48e5d Refactor ALU code into its own module, and fix things. 
* Fix overflow flag being ignored
* Fix barrel shifter misimplementations
* Rustfmt fixes


Former-commit-id: a14d50372f7850a04b204accf4e5d8b924e4b48e
 2019-07-08 20:57:58 +03:00
Michel Heily ecdd6e0ed4 thumb: Fix ALU ops for barrel shifter opcodes 
I kinda missed these when I read the manual ><


Former-commit-id: 7d6c21b6c3b46bf065a177c1c7f7a7a1baa6b8fa
 2019-07-08 01:47:41 +03:00
Michel Heily 163d8bda59 Fix not flushing the pipeline for "mov pc, reg" instructions 
Former-commit-id: 66136ef70b8f48d5e9f4c10b65f1e2fbd3dd3ea1
 2019-07-08 00:58:09 +03:00
Michel Heily 863838a4a4 Force R15 alignment via cpu.set_reg 
I've encounted many bugs with instructions that write PC but don't align
it.


Former-commit-id: b6a234564729f83c0b5e8adfa293227299aad4ac
 2019-07-08 00:57:18 +03:00
Michel Heily 7e7d2c5208 thumb: Fix misimplementation of THUMB 12 :( 
And this kids, is why you don't ever assume what an instruction does
without reading the manual.
Also, I called the ThumbFormat enum variant "LdrAddress", so I went
ahead and implemented as an ldr_str :/


Former-commit-id: f13833d16fba07565a0aba9d247d9754dbfc3d39
 2019-07-08 00:49:03 +03:00
Michel Heily 6eab76d52f Impose a minimum length of 4MB for the gamepak memory 
Former-commit-id: 08e66bff0bc39968e572b941da84c155a45f31c8
 2019-07-07 23:33:47 +03:00
Michel Heily d36da30618 arm: Impl LDR_STR_HS 
Former-commit-id: 2baa0f2fb8cf855cb4626fbb1937e17f4e7d3035
 2019-07-07 23:10:17 +03:00
Michel Heily 45f3bd6264 arm: Fix STR use of R15 as the base register (Rd) 
Former-commit-id: 696733731a9996ebb90b7d4acf3341facc1ed228
 2019-07-07 22:57:21 +03:00
Michel Heily c92bde54a1 Begin modeling DMA 
Former-commit-id: 83ab601e70666f76ed3ebfb22340c6b1868af3ac
 2019-07-07 01:47:51 +03:00
Michel Heily c2685c14d7 Impl more thumb, Fix more things, the usual 
Former-commit-id: 02f1898bfd8dd50519f103bb367e358fc55c46e7
 2019-07-06 23:38:08 +03:00
Michel Heily 6dd48c6238 Add option to skip bios code so I can start checking out test roms 
Former-commit-id: b78c8d9807ba3097d641a57ec7fcd500b32b4d96
 2019-07-06 19:26:51 +03:00
Michel Heily 36dba78c55 More fixes 
Former-commit-id: 897cbc0fb9c12469606c48ee8a02d35bf82c2ae5
 2019-07-06 18:48:22 +03:00
Michel Heily 8dc169d25d fix: bug in some ALU opcodes 
Former-commit-id: 7e05a11a709ad7f834916afa82ec5460068363f9
 2019-07-06 18:47:42 +03:00
Michel Heily efb5d361d6 Add PaletteView command for the debugger. 
Former-commit-id: c4e0250eea700cfbcbb9f904cde7b6bc055d3e05
 2019-07-06 16:04:43 +03:00
Michel Heily 3cc84b1b03 Model many things 
Former-commit-id: b87fa2b16b395f497cf217ea043e68404ab2f65e
 2019-07-06 15:54:07 +03:00
Michel Heily d1ef35646f Impl Thumb LdrStrImmOffset 
Former-commit-id: 17d6f4ae1cb5f68b9fccf35536a6346e88326e77
 2019-07-06 15:51:58 +03:00
Michel Heily 600bebc9d2 Partially Impl Arm LDM_STM (give me a break) 
Manually testing seems to work, too lazy to write any tests now,
Will do it after all instructions are complete, buggy or not.


Former-commit-id: 0f36c81d6451c706408dd3c4815bfb3abea1ff44
 2019-07-05 18:39:10 +03:00
Michel Heily 4da863da9b Fix carry flag on barrel shifter ops 
Former-commit-id: 31cf2166d97fcdcca0dd9c59591f5e28b5b5f6cc
 2019-07-05 18:31:08 +03:00
Michel Heily 638e449421 Impl Thumb 18 (Branch) 
Former-commit-id: 152dab739a1fa1b9d324084fc810b8540af9c3d7
 2019-07-05 16:21:24 +03:00
Michel Heily 74329c2a0b Never leave unfinished work.. 
Former-commit-id: 91acecdaf3ec7f9de892bd9f712e3cf521e08beb
 2019-07-05 16:10:21 +03:00
Michel Heily 0c50209735 Fix wrong calculation of conditional branch offset in Thumb mode 
Former-commit-id: 4cc28b13b19b2bf45e2b0e34d9a9dc0f83f82b01
 2019-07-05 16:01:16 +03:00
Michel Heily 37117257a6 Impl Thumb 10 (load store halfword) 
Former-commit-id: 0d5e88f200613b6df2b999ecbb855ce480e73322
 2019-07-05 15:50:14 +03:00
Michel Heily d4b6952411 Impl Thumb 19, fix warnings and rustfmt 
Former-commit-id: 8690aa25b1aa343b344776716b6213596bd1459a
 2019-07-05 15:34:52 +03:00
Michel Heily fb0d3acb14 Impl Thumb Format 1 untested 
Former-commit-id: e80617fd415ba951310a42c79b6ca37251d0e250
 2019-07-05 14:09:04 +03:00
Michel Heily 058760d7e4 Impl thumb Format4 
Former-commit-id: 7b8705ee7b76bbeb5b2a21e830d16db06ce8d63c
 2019-07-05 13:58:26 +03:00
Michel Heily 01290f6a28 Impl Thumb LdrStrSp 
Untested.


Former-commit-id: 8fa842d4969e30247fc1706dfe053c7dfbb37843
 2019-07-05 13:20:37 +03:00
Michel Heily be9499c76d Move cycle counting to CPU Core 
This isn't accurate, I'm probably missing something but at least it'll
make the instruction implementation more clean for now..


Former-commit-id: de24b15e1a51e1998207e5ea96fc8543f2553a26
 2019-07-05 13:08:07 +03:00
Michel Heily f8ebe26e5e Implement thumb format 13 
(NOT TESTED)


Former-commit-id: 160ee3a6c09a12cab53f69c94b385ea17666bd5f
 2019-07-05 03:46:04 +03:00
Michel Heily 5df9b6f317 Add thumb push-pop. 
Not tested, cycle modeling is crap


Former-commit-id: a5092dab79a1a660fc6c96a71f0908cc2054be27
 2019-07-05 03:28:02 +03:00
Michel Heily e66a8a9a3b Fix LR again :( 
Former-commit-id: 820315154ae58dcc29c4a8921094598f149b0255
 2019-07-05 03:27:23 +03:00
Michel Heily 2293300260 Add test for the bug fixed on e2a1303 
Former-commit-id: 98d0789aaf92a549cbe1b387461fd9acd4d773c0
 2019-07-04 02:06:41 +03:00
Michel Heily 702a08e30c Add many thumb instructions.. 
TODO add more tests for all the instructions I've got implemented so
far.
Also, I need to rewrite the whole "sysbus" module again because it's
crap and I keep refactoring it as I go.
I've added the "Dummy" because the bios for some reason tries to memzero
an unmapped region on the work ram (the thumb loop that ends at 0x126)


Former-commit-id: 67befd0935ee10df9ac8ceeaebd14f69767a7f16
 2019-07-04 01:56:50 +03:00
Michel Heily 984b17fa39 Fix arm mode STR insn 
Former-commit-id: 80903a9054e9b0dac07a5e2bb3cff7b0e722d438
 2019-07-04 01:56:11 +03:00
Michel Heily 923032f8cf REPL UI changes 
Former-commit-id: 6852b86541f967785dbffb6833fc2c11fa5dbef3
 2019-07-04 01:37:47 +03:00
Michel Heily 3541779fbf Fix LR when changing cpu modes 
Former-commit-id: 0ac911ee90758b9bffaafd459f1d9bca86d5064d
 2019-07-04 01:37:05 +03:00
Michel Heily 6a3d4358da Update .launch.json 
Former-commit-id: c922a1358c2a048d69c38e60734fc00ffa78a4a0
 2019-07-04 01:36:41 +03:00
= 28743702a1 Update waitstates for 256k work ram 
Former-commit-id: f5680c90e4ab4a9b29899cd5e0fe316d8227fc24
 2019-07-03 11:30:00 +03:00
MishMish c9df623d36 Update README.md 
Former-commit-id: 03b224b7de9735a1ed43dd7460fe5fa9ece147b4
 2019-07-03 02:23:36 +03:00
Michel Heily eaf972de93 Implement thumb format 6 (PC-Relative Load) and test it. 
Former-commit-id: ae161edb0c8968913d2ef72a14053c118c6f7692
 2019-07-03 02:15:16 +03:00
Michel Heily 58e1230e7a Model the cartidge. 
Former-commit-id: b51d2928631bfc438b9f1b15fafcaa9d90008179
 2019-07-03 01:40:08 +03:00
Michel Heily b82874809f Implement thumb format3 instruction and add a test for it. 
Former-commit-id: 8cf6664027dc3d5dbeb6d2ca3d089820baac2709
 2019-07-03 01:26:48 +03:00
Michel Heily 4011911cca Pass around "Bus" instead of "SysBus" 
Former-commit-id: c20dae7dd3ddcb3bd8f671a16fd67a241bd6c459
 2019-07-03 01:22:36 +03:00
Michel Heily 6f81c236a6 Mega Commit #2 - Add some thumb decoding and disassembly 
Former-commit-id: e3a89ac681a8d6f6f0bee85b32f64d181e11242f
 2019-07-03 00:03:35 +03:00
Michel Heily cbddeffd91 arm: Implement MSR_REG and fix some prefetching errors 
Former-commit-id: 177b8966159ed86472b0d4d031363df72d46807a
 2019-07-02 16:53:29 +03:00
Michel Heily 05fb40c17c debugger: Add Deref expression. 
i.e:
r5 = *r6
r5 = *(u8*)r6
r5 = *(u16*)0x08000000


Former-commit-id: 962dade8e3c0b9f291115285137cf51b0abde266
 2019-07-02 13:36:52 +03:00
Michel Heily 645e71ac40 Remove garbage file 
Former-commit-id: 906b8bc6f6b95ddc3565043ff4406a403e7ba08a
 2019-07-01 19:26:52 +03:00