Michel Heily
be9499c76d
Move cycle counting to CPU Core
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This isn't accurate, I'm probably missing something but at least it'll
make the instruction implementation more clean for now..
Former-commit-id: de24b15e1a51e1998207e5ea96fc8543f2553a26
2019-07-05 13:08:07 +03:00
Michel Heily
984b17fa39
Fix arm mode STR insn
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Former-commit-id: 80903a9054e9b0dac07a5e2bb3cff7b0e722d438
2019-07-04 01:56:11 +03:00
Michel Heily
eaf972de93
Implement thumb format 6 (PC-Relative Load) and test it.
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Former-commit-id: ae161edb0c8968913d2ef72a14053c118c6f7692
2019-07-03 02:15:16 +03:00
Michel Heily
b82874809f
Implement thumb format3 instruction and add a test for it.
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Former-commit-id: 8cf6664027dc3d5dbeb6d2ca3d089820baac2709
2019-07-03 01:26:48 +03:00
Michel Heily
4011911cca
Pass around "Bus" instead of "SysBus"
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Former-commit-id: c20dae7dd3ddcb3bd8f671a16fd67a241bd6c459
2019-07-03 01:22:36 +03:00
Michel Heily
6f81c236a6
Mega Commit #2 - Add some thumb decoding and disassembly
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Former-commit-id: e3a89ac681a8d6f6f0bee85b32f64d181e11242f
2019-07-03 00:03:35 +03:00
Michel Heily
cbddeffd91
arm: Implement MSR_REG and fix some prefetching errors
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Former-commit-id: 177b8966159ed86472b0d4d031363df72d46807a
2019-07-02 16:53:29 +03:00
Michel Heily
70179984d0
cpu: arm: Fix alu_add_update_carry function
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Woopsie
Former-commit-id: 2da74e4bfd4b59a2885519a99f4b2c3d83031ee2
2019-07-01 19:25:42 +03:00
Michel Heily
2081b70ee2
cpu: arm: Fix R14 for branch with link instruction
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Former-commit-id: bc927d86e5a170b0e4568b4ceeb7832d23ad309c
2019-07-01 19:24:52 +03:00
Michel Heily
ea8c4f2a60
Refactor ArmInstructionFormat => ArmFormat
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Former-commit-id: 0ba6e1e6efedad55b2716b3f2ab5a2a629dd18a5
2019-07-01 17:51:07 +03:00
Michel Heily
6b225d776d
Implement all memory mappings. Reformat many files.
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Former-commit-id: c0a62b610e62d2db2a4daf4aeef40068820daa52
2019-07-01 17:45:29 +03:00
Michel Heily
bd053354cb
Implement LDR/STR (not tested) and add cycle counting
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Former-commit-id: ec9e6bfc2a94291e47d41ff7d839007879d3d694
2019-06-30 16:59:37 +03:00
Michel Heily
967ccca8dd
Mega commit - model CPU pipelining.
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I except many bugs to arise..
Former-commit-id: bcc6ea57af803f783b0dd548b50956b3ccda2b1a
2019-06-29 22:23:12 +03:00
Michel Heily
bd7fd472cf
arm: Add tests for ldr/str
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And also test disassembling while at it..
2019-06-28 12:36:19 +03:00
Michel Heily
d11620e65b
cpu: Add SWI instruction
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Also cleanup code, and add a test for swi decoding
2019-06-28 11:46:36 +03:00
Michel Heily
1a0725f1a3
cpu: Model exceptions
2019-06-27 15:13:38 +03:00
Michel Heily
6552329310
cpu: Kinda implement data processing instructions
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When I say "Kinda", I mean that it is not tested well.
2019-06-27 13:16:00 +03:00
Michel Heily
e5d93f689f
Work..
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Refactor disassembler to a struct.
Implement more commands;
2019-06-27 13:15:34 +03:00
Michel Heily
22a915ec85
Add continue command
2019-06-27 13:15:34 +03:00
