Michel Heily
fb5229705b
Refactor and fix arm condition check
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Former-commit-id: 132c14fc56a21426263971e2d544ff10f072fea1
2019-07-13 23:32:43 +03:00
Michel Heily
1747addcd3
Start modeling the Lcd Display
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Former-commit-id: 544f185c6f9eead870032170292b1cc8afc724bf
2019-07-11 18:17:28 +03:00
Michel Heily
95f45e55a9
arm: Impl MULL_MLAL and fix writeback for post-index memory transfers
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Also some minor fixes and formatting
Former-commit-id: 4929b28cbb4eeeed5acfbdcdd19392ffa3bb0f37
2019-07-11 18:10:58 +03:00
Michel Heily
4763f79abf
arm: Impl MLA
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Former-commit-id: fe2c836bd09af165381537445dd288ca7bac24ce
2019-07-11 00:02:39 +03:00
Michel Heily
5bc4c79d6e
arm: Implement MRS
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Former-commit-id: 8c1528b2bcd08096f929c4ee940f1a1f5eac2911
2019-07-10 23:54:45 +03:00
Michel Heily
5f625b2209
Add special case for MSR immediate
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Former-commit-id: f9fabb3c0d7c05243866b712096c2c82cf41672d
2019-07-10 23:48:14 +03:00
Michel Heily
a9bf2d25e0
arm: Implement Arm MSR_FLAGS
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Former-commit-id: 64d2cf255304ecca02dadc55266d22bc1f92bb4c
2019-07-10 22:35:40 +03:00
Michel Heily
4c3379615a
Fix bug in RRX (defined "old_carry" after changing it >< )
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Former-commit-id: b890d40bb57da1cc6b63d6436bc8f346131fa5bc
2019-07-10 22:35:40 +03:00
Michel Heily
50086a8715
Fix word alignment for arm BX
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Former-commit-id: 9223259793cd8ecccb02b40c428d32315c632bff
2019-07-10 22:35:40 +03:00
Michel Heily
2864f83681
Arm: Partially implement MUL
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Former-commit-id: 3b37f5cbe327e15be4cee56572c2230dbda48082
2019-07-10 22:35:40 +03:00
Tamir
543161d6b8
Fix cli help lines to all follow the same structure
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Help lines all start with a capital letter and don't end with a dot
Former-commit-id: 31e65514d15540538e2de528810957e16c8b5090
2019-07-10 12:59:48 +03:00
Michel Heily
92f65794d8
Fix writeback for Thumb LdmStm
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Former-commit-id: 00a15dc99716290da7b260b261090454d621ce8a
2019-07-09 02:20:32 +03:00
Michel Heily
65de0c4e9d
Thumb 4 - Take care of "neg" case.
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I overlooked it :/
Former-commit-id: 360eb755bcf343cddd98807e9faeff007c94cf64
2019-07-09 01:30:24 +03:00
Michel Heily
34233fa654
alu: Fix bug in SBC and RSC ops
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Former-commit-id: 1cb23d6280e1816395c46a7571dd9f48df870202
2019-07-09 01:29:34 +03:00
Michel Heily
19e4196384
Thumb 4 - Set flags if needed (For CMP)
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Former-commit-id: 4f5bc97375c8aa45036b025a3420331a8137da17
2019-07-09 01:28:14 +03:00
Michel Heily
0bdf4993ee
thumb: Word align PC when jumping to Arm code
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Former-commit-id: 55fa28246c45a6bd807c53ce8bf0bb5865d36564
2019-07-09 01:27:23 +03:00
Michel Heily
6ddb136852
alu: Also fix carry detection for unsigned addition
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Former-commit-id: d405f885e2b54c23aef5faab86cc1da681bd05ec
2019-07-09 00:40:52 +03:00
Michel Heily
6c0df33597
Finally got the barrel shifter right?
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The barrel shifter sure has lots of edge cases, need to implement tests ASAP
Former-commit-id: 989fc4477f610603154404d0ed4335619ebd6345
2019-07-09 00:33:53 +03:00
Michel Heily
2817db4e1c
alu: Fix carry detection for subtraction
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Former-commit-id: c9d8612f72ce4a002ea33446209bd7e6da0eb5aa
2019-07-09 00:33:53 +03:00
Michel Heily
1bacb927af
Fix ROR with amount > 32
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Former-commit-id: 8f88de3c55c0e452266c40944ff920175b83627e
2019-07-08 21:03:47 +03:00
Michel Heily
9421281381
Fix THUMB 1
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I didn't send this through the ALU :/
Former-commit-id: 40b4d23dcd769496e9dcd47bbf8d472b91e6a7bf
2019-07-08 20:58:22 +03:00
Michel Heily
f7b2b48e5d
Refactor ALU code into its own module, and fix things.
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* Fix overflow flag being ignored
* Fix barrel shifter misimplementations
* Rustfmt fixes
Former-commit-id: a14d50372f7850a04b204accf4e5d8b924e4b48e
2019-07-08 20:57:58 +03:00
Michel Heily
ecdd6e0ed4
thumb: Fix ALU ops for barrel shifter opcodes
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I kinda missed these when I read the manual ><
Former-commit-id: 7d6c21b6c3b46bf065a177c1c7f7a7a1baa6b8fa
2019-07-08 01:47:41 +03:00
Michel Heily
163d8bda59
Fix not flushing the pipeline for "mov pc, reg" instructions
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Former-commit-id: 66136ef70b8f48d5e9f4c10b65f1e2fbd3dd3ea1
2019-07-08 00:58:09 +03:00
Michel Heily
863838a4a4
Force R15 alignment via cpu.set_reg
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I've encounted many bugs with instructions that write PC but don't align
it.
Former-commit-id: b6a234564729f83c0b5e8adfa293227299aad4ac
2019-07-08 00:57:18 +03:00
Michel Heily
7e7d2c5208
thumb: Fix misimplementation of THUMB 12 :(
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And this kids, is why you don't ever assume what an instruction does
without reading the manual.
Also, I called the ThumbFormat enum variant "LdrAddress", so I went
ahead and implemented as an ldr_str :/
Former-commit-id: f13833d16fba07565a0aba9d247d9754dbfc3d39
2019-07-08 00:49:03 +03:00
Michel Heily
6eab76d52f
Impose a minimum length of 4MB for the gamepak memory
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Former-commit-id: 08e66bff0bc39968e572b941da84c155a45f31c8
2019-07-07 23:33:47 +03:00
Michel Heily
d36da30618
arm: Impl LDR_STR_HS
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Former-commit-id: 2baa0f2fb8cf855cb4626fbb1937e17f4e7d3035
2019-07-07 23:10:17 +03:00
Michel Heily
45f3bd6264
arm: Fix STR use of R15 as the base register (Rd)
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Former-commit-id: 696733731a9996ebb90b7d4acf3341facc1ed228
2019-07-07 22:57:21 +03:00
Michel Heily
c92bde54a1
Begin modeling DMA
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Former-commit-id: 83ab601e70666f76ed3ebfb22340c6b1868af3ac
2019-07-07 01:47:51 +03:00
Michel Heily
c2685c14d7
Impl more thumb, Fix more things, the usual
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Former-commit-id: 02f1898bfd8dd50519f103bb367e358fc55c46e7
2019-07-06 23:38:08 +03:00
Michel Heily
6dd48c6238
Add option to skip bios code so I can start checking out test roms
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Former-commit-id: b78c8d9807ba3097d641a57ec7fcd500b32b4d96
2019-07-06 19:26:51 +03:00
Michel Heily
36dba78c55
More fixes
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Former-commit-id: 897cbc0fb9c12469606c48ee8a02d35bf82c2ae5
2019-07-06 18:48:22 +03:00
Michel Heily
8dc169d25d
fix: bug in some ALU opcodes
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Former-commit-id: 7e05a11a709ad7f834916afa82ec5460068363f9
2019-07-06 18:47:42 +03:00
Michel Heily
efb5d361d6
Add PaletteView command for the debugger.
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Former-commit-id: c4e0250eea700cfbcbb9f904cde7b6bc055d3e05
2019-07-06 16:04:43 +03:00
Michel Heily
3cc84b1b03
Model many things
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Former-commit-id: b87fa2b16b395f497cf217ea043e68404ab2f65e
2019-07-06 15:54:07 +03:00
Michel Heily
d1ef35646f
Impl Thumb LdrStrImmOffset
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Former-commit-id: 17d6f4ae1cb5f68b9fccf35536a6346e88326e77
2019-07-06 15:51:58 +03:00
Michel Heily
600bebc9d2
Partially Impl Arm LDM_STM (give me a break)
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Manually testing seems to work, too lazy to write any tests now,
Will do it after all instructions are complete, buggy or not.
Former-commit-id: 0f36c81d6451c706408dd3c4815bfb3abea1ff44
2019-07-05 18:39:10 +03:00
Michel Heily
4da863da9b
Fix carry flag on barrel shifter ops
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Former-commit-id: 31cf2166d97fcdcca0dd9c59591f5e28b5b5f6cc
2019-07-05 18:31:08 +03:00
Michel Heily
638e449421
Impl Thumb 18 (Branch)
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Former-commit-id: 152dab739a1fa1b9d324084fc810b8540af9c3d7
2019-07-05 16:21:24 +03:00
Michel Heily
74329c2a0b
Never leave unfinished work..
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Former-commit-id: 91acecdaf3ec7f9de892bd9f712e3cf521e08beb
2019-07-05 16:10:21 +03:00
Michel Heily
0c50209735
Fix wrong calculation of conditional branch offset in Thumb mode
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Former-commit-id: 4cc28b13b19b2bf45e2b0e34d9a9dc0f83f82b01
2019-07-05 16:01:16 +03:00
Michel Heily
37117257a6
Impl Thumb 10 (load store halfword)
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Former-commit-id: 0d5e88f200613b6df2b999ecbb855ce480e73322
2019-07-05 15:50:14 +03:00
Michel Heily
d4b6952411
Impl Thumb 19, fix warnings and rustfmt
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Former-commit-id: 8690aa25b1aa343b344776716b6213596bd1459a
2019-07-05 15:34:52 +03:00
Michel Heily
fb0d3acb14
Impl Thumb Format 1 untested
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Former-commit-id: e80617fd415ba951310a42c79b6ca37251d0e250
2019-07-05 14:09:04 +03:00
Michel Heily
058760d7e4
Impl thumb Format4
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Former-commit-id: 7b8705ee7b76bbeb5b2a21e830d16db06ce8d63c
2019-07-05 13:58:26 +03:00
Michel Heily
01290f6a28
Impl Thumb LdrStrSp
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Untested.
Former-commit-id: 8fa842d4969e30247fc1706dfe053c7dfbb37843
2019-07-05 13:20:37 +03:00
Michel Heily
be9499c76d
Move cycle counting to CPU Core
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This isn't accurate, I'm probably missing something but at least it'll
make the instruction implementation more clean for now..
Former-commit-id: de24b15e1a51e1998207e5ea96fc8543f2553a26
2019-07-05 13:08:07 +03:00
Michel Heily
f8ebe26e5e
Implement thumb format 13
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(NOT TESTED)
Former-commit-id: 160ee3a6c09a12cab53f69c94b385ea17666bd5f
2019-07-05 03:46:04 +03:00
Michel Heily
5df9b6f317
Add thumb push-pop.
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Not tested, cycle modeling is crap
Former-commit-id: a5092dab79a1a660fc6c96a71f0908cc2054be27
2019-07-05 03:28:02 +03:00