Michel Heily
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984b17fa39
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Fix arm mode STR insn
Former-commit-id: 80903a9054e9b0dac07a5e2bb3cff7b0e722d438
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2019-07-04 01:56:11 +03:00 |
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Michel Heily
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923032f8cf
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REPL UI changes
Former-commit-id: 6852b86541f967785dbffb6833fc2c11fa5dbef3
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2019-07-04 01:37:47 +03:00 |
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Michel Heily
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3541779fbf
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Fix LR when changing cpu modes
Former-commit-id: 0ac911ee90758b9bffaafd459f1d9bca86d5064d
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2019-07-04 01:37:05 +03:00 |
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Michel Heily
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eaf972de93
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Implement thumb format 6 (PC-Relative Load) and test it.
Former-commit-id: ae161edb0c8968913d2ef72a14053c118c6f7692
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2019-07-03 02:15:16 +03:00 |
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Michel Heily
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b82874809f
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Implement thumb format3 instruction and add a test for it.
Former-commit-id: 8cf6664027dc3d5dbeb6d2ca3d089820baac2709
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2019-07-03 01:26:48 +03:00 |
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Michel Heily
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4011911cca
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Pass around "Bus" instead of "SysBus"
Former-commit-id: c20dae7dd3ddcb3bd8f671a16fd67a241bd6c459
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2019-07-03 01:22:36 +03:00 |
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Michel Heily
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6f81c236a6
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Mega Commit #2 - Add some thumb decoding and disassembly
Former-commit-id: e3a89ac681a8d6f6f0bee85b32f64d181e11242f
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2019-07-03 00:03:35 +03:00 |
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Michel Heily
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cbddeffd91
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arm: Implement MSR_REG and fix some prefetching errors
Former-commit-id: 177b8966159ed86472b0d4d031363df72d46807a
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2019-07-02 16:53:29 +03:00 |
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Michel Heily
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05fb40c17c
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debugger: Add Deref expression.
i.e:
r5 = *r6
r5 = *(u8*)r6
r5 = *(u16*)0x08000000
Former-commit-id: 962dade8e3c0b9f291115285137cf51b0abde266
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2019-07-02 13:36:52 +03:00 |
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Michel Heily
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645e71ac40
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Remove garbage file
Former-commit-id: 906b8bc6f6b95ddc3565043ff4406a403e7ba08a
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2019-07-01 19:26:52 +03:00 |
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Michel Heily
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70179984d0
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cpu: arm: Fix alu_add_update_carry function
Woopsie
Former-commit-id: 2da74e4bfd4b59a2885519a99f4b2c3d83031ee2
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2019-07-01 19:25:42 +03:00 |
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Michel Heily
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2081b70ee2
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cpu: arm: Fix R14 for branch with link instruction
Former-commit-id: bc927d86e5a170b0e4568b4ceeb7832d23ad309c
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2019-07-01 19:24:52 +03:00 |
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Michel Heily
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ea8c4f2a60
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Refactor ArmInstructionFormat => ArmFormat
Former-commit-id: 0ba6e1e6efedad55b2716b3f2ab5a2a629dd18a5
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2019-07-01 17:51:07 +03:00 |
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Michel Heily
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6b225d776d
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Implement all memory mappings. Reformat many files.
Former-commit-id: c0a62b610e62d2db2a4daf4aeef40068820daa52
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2019-07-01 17:45:29 +03:00 |
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Michel Heily
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bd053354cb
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Implement LDR/STR (not tested) and add cycle counting
Former-commit-id: ec9e6bfc2a94291e47d41ff7d839007879d3d694
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2019-06-30 16:59:37 +03:00 |
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Michel Heily
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98eee121fc
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Correct F flag behaviour when entrying an exception.
Former-commit-id: b0ef6352d9f0c027657c6e5eeb615a131e9523d2
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2019-06-29 23:01:23 +03:00 |
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Michel Heily
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967ccca8dd
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Mega commit - model CPU pipelining.
I except many bugs to arise..
Former-commit-id: bcc6ea57af803f783b0dd548b50956b3ccda2b1a
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2019-06-29 22:23:12 +03:00 |
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Michel Heily
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3429b67c41
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Fix test_decode_branch_backwards failing
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2019-06-28 13:09:30 +03:00 |
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Michel Heily
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bd7fd472cf
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arm: Add tests for ldr/str
And also test disassembling while at it..
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2019-06-28 12:36:19 +03:00 |
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Michel Heily
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7898bf61f3
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arm: Fix bug when calculating 24bit branch offsets, and add a test for
it.
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2019-06-28 12:01:49 +03:00 |
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Michel Heily
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d11620e65b
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cpu: Add SWI instruction
Also cleanup code, and add a test for swi decoding
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2019-06-28 11:46:36 +03:00 |
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Michel Heily
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1a0725f1a3
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cpu: Model exceptions
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2019-06-27 15:13:38 +03:00 |
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Michel Heily
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1d766e95de
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cpu: Fix bug in psr mode bits
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2019-06-27 15:03:44 +03:00 |
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Michel Heily
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6552329310
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cpu: Kinda implement data processing instructions
When I say "Kinda", I mean that it is not tested well.
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2019-06-27 13:16:00 +03:00 |
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Michel Heily
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5808c03fcd
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cpu: Model Program Status Register.
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2019-06-27 13:15:46 +03:00 |
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Michel Heily
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e5d93f689f
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Work..
Refactor disassembler to a struct.
Implement more commands;
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2019-06-27 13:15:34 +03:00 |
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Michel Heily
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22a915ec85
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Add continue command
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2019-06-27 13:15:34 +03:00 |
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Michel Heily
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9921f1c974
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Add info and reset commands
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2019-06-27 13:15:34 +03:00 |
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Michel Heily
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9330c53957
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Start modeling CPU
Wrote a shallow skeleton of a CPU Core.
Finally made the disassembler a clap subcommand.
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2019-06-27 13:15:19 +03:00 |
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Michel Heily
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addea1efa0
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Merge both packages
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2019-06-24 22:02:00 +03:00 |
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