Commit graph

71 commits

Author SHA1 Message Date
Michel Heily 12d9edf5c4 Fix some cargo-clippy, and broken sub-crates
Former-commit-id: 93db7bc11bff9a48f4d66e0a378cd77ab42ca197
Former-commit-id: a6ce714c2a6a4112ff30d748c0686b1b2da41c6b
2022-09-05 00:34:00 +03:00
Michel Heily 28fb9ffa70 chore: Refactor into crates
Been wanting to do this for a long time.
This does impose performance issues when building with the vanilla
release profile, as cargo does not perform optimizations across crate
boundary (we care mostly about inlining).
so I added release-lto profile

Also fixed some broken stuff I found across the project, meh


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2022-09-04 23:54:44 +03:00
Michel Heily 91453e8777 Refactor&improve the scheduler to handle missed events
Solves #168


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Former-commit-id: e07219e40fa187f516dd266ab753a67f3c7e796b
2022-09-04 02:51:44 +03:00
Michel Heily 47032ec8b9 arm: Forgot this one :)
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Former-commit-id: 4001761f719b98ed98d652ee00275dd1d8f7d232
2021-07-04 00:36:21 +03:00
Michel Heily 76d9102231 arm: remove old code
Former-commit-id: 906a5b902726c000fcdc1a01443c6662da72b2c9
Former-commit-id: ab2dac2ae2c066758645026b6484cd1a9355831a
2021-07-03 22:29:55 +03:00
Michel Heily a7cc770be8 arm: finish converting all instructions to const-generics
Former-commit-id: 4557ecffb89d563357f5bd769515254533a404ac
Former-commit-id: 8ce461f1b48ff5e7c72cdcd3069dcee0960dbc8e
2021-07-03 22:29:55 +03:00
Michel Heily 86c35a2eb3 arm: do const-generics for BlockDataTransfer
Former-commit-id: d4be9648b334891de5a2daf3c2931cf8e31b337a
Former-commit-id: 6e7e54efd9fa3901008d2fab21dab4560d597763
2021-07-03 22:29:55 +03:00
Michel Heily 416cc2937b arm: do const-generics for HalfwordDataTransfer*
Former-commit-id: 891fd23bef3a4ecc7fe5a4012456d51fc91f8601
Former-commit-id: 431ac09cbf73078988d6400c6320a7fdadceef1a
2021-07-03 22:29:55 +03:00
Michel Heily 9819bf611d arm: convert some instructions to const-generics
Former-commit-id: 493127ef64f3d5e396e0391c5bb0db985cac8945
Former-commit-id: 987edb22cd27584dfdee0a23602df45424a6f4b8
2021-07-03 22:29:55 +03:00
Michel Heily 03d28c77b6 thumb: Finish converting all instructions to use const-generics
Former-commit-id: 671c75a985123a52b312a8ae5495ff545d7678dc
Former-commit-id: c0794ce36f410cd8c058cbe087c388a84aae8b85
2021-07-03 22:29:55 +03:00
Michel Heily 4a7eb53707 thumb: more const-generics :)
Former-commit-id: e869dafa68973d944be3b8d88d3238451b64718c
Former-commit-id: 8118d529e7a40303e4535f581ad4cf247b926b46
2021-07-03 22:29:55 +03:00
Michel Heily 9e6b787536 arm: convert more instructions to use const generics
Former-commit-id: bd4c802a49a8c37e6709c2481cc73367bbadade0
Former-commit-id: f3881e4f8fee1a7110cf676c3c62b6c39db88280
2021-07-03 22:29:55 +03:00
Michel Heily 7e96be21ae perf: Move pc to the beginning of the CPU struct
Former-commit-id: 1b17095bee5c6010d3792fc220a8abcf3a373207
Former-commit-id: 5e65dad6398ef6e9d907d086c982fd70e85c9184
2021-07-03 22:29:55 +03:00
Michel Heily 892dfbe395 More const generics..
Former-commit-id: 74e4c88128d8c83bbb23a874ba8e0821ffc583a7
Former-commit-id: 99ed5c5f73ba9ad2e95b9b190e0100d0e1b9e6a2
2021-07-03 22:29:55 +03:00
Michel Heily 0665ff7451 WIP 2 SingleDataTransfer
Former-commit-id: 8a103161f34eb1a6c731c63ae65ca1056117ec55
Former-commit-id: 74c8158e7354253f6bd4ad50488d34de34e3ad70
2021-07-03 22:29:55 +03:00
Michel Heily b3c3c70bce WIP const generics
Former-commit-id: 2c38215fb57de66bfce26cfa7e61c460bd2954ac
Former-commit-id: 8fe5cc4fdc58b1155590dbfd6546b280fcdcc259
2021-07-03 22:29:55 +03:00
Michel Heily 1545be7b4f core: debugger: Improve info command
Former-commit-id: 534b4907911408f3765825145f14d0b680058dcf
Former-commit-id: 20ed0d130e2fb17b9fc6fb7c1cfc485277a6fb10
2021-06-10 00:13:17 +03:00
Michel Heily 82fa433e26 Fix warning: invalid attribute
Former-commit-id: d3a6a4f23c343ba9960269938e1127729271545d
Former-commit-id: 0fc0461c38531a8a841d7dbab14dd4796ab3a77b
2021-06-09 23:39:43 +03:00
Michel Heily 7512bad3a0 core: debugger: Fix dissassembly
Former-commit-id: ec8d6726eb1f599e43b0826e99508cc954454220
Former-commit-id: 3b64d5b60377c303b85be32794df18671002d509
2021-06-09 02:24:51 +03:00
Michel Heily 626c5fa805 core: arm7tdmi: Fix new bug in LDR/STR introduced in b603904.
Of course only arm-wrestler caught it while mgba suite/eggvance did not :(


Former-commit-id: a5dcaa9b40c8a5a5d5fb1e531a601361869a041f
Former-commit-id: eb8d30a3c1cf9c39425b29e6d8386ac2b68a424b
2021-06-09 02:01:47 +03:00
Michel Heily 97704f2621 core: debugger: Fix traces
Former-commit-id: fbdaef86e2164ad1eeb5267041070958c024ceda
Former-commit-id: 643bcfe7ebccf77297d2371715490b3005e91d92
2021-06-09 02:01:42 +03:00
Michel Heily ff472db249 core: debugger: Use mut references for GameBoyAdvance
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Former-commit-id: f6be5b7940c4f3d517fa564830be607321ade534
2021-06-09 01:24:31 +03:00
Michel Heily f140e0f83b core: Fix broken debugger build
Former-commit-id: 0dcdb6d758e463eecc02faf5a0e7eff6c8c08899
Former-commit-id: 5e9d842158d573b10dc1ddb4c3621056282351ed
2021-06-09 01:08:42 +03:00
Michel Heily 20506091cc [perf] arm: Improve performance with barrel shifter.
Instead of using a struct member to hold the last barrel shifter carry output, which is expansive as it needs to be saved/loaded from memory, I now pass the carry around as an INOUT parameter.
Using perf anotate really shows high perctile of samples being spent on reading/writing `self.bs_carry_out`

Since this is a rather "surgical" changeset, I have made sure to run it against eggvance test suite, mGBA test suite and some games as well.

I actually saw better improvements than what the benchmark measured, but 7% is decent enough :)

```
run_60_frames           time:   [180.18 ms 180.45 ms 180.77 ms]
                        change: [-7.2464% -6.9081% -6.6324%] (p = 0.00 < 0.05)
                        Performance has improved.
```


Former-commit-id: 7cd7105a07aa0b78cab9dc8bbae3682b02b7ab7c
Former-commit-id: c68514beb3fa6c34f5f65544acbead21e527dbb0
2021-06-05 18:54:46 +03:00
Michel Heily 21708a3d58 [perf] sysbus: Improve add_cycls()
Fulfill TODO from long ago, I used perf-record (--call-graph dwarf)  and detected that add_cycles() was hot enough,
I added 2 optimizations:
- Removed bound checks from array accesses
- Increase the LUT size to include dummy entries for open-bus to eliminate the if check

run_60_frames           time:   [183.65 ms 183.69 ms 183.73 ms]
                        change: [-9.4414% -9.2849% -9.1315%] (p = 0.00 < 0.05)
                        Performance has improved.


Former-commit-id: 1cbb596b856e604ad6c48eb0d47771e7cee44d1e
Former-commit-id: 9f15e35237f343d0c816fd9d51d81081736d9e17
2021-06-05 17:31:10 +03:00
Michel Heily cb2b97e0c7 [perf] core: arm7tdmi: Re-arange some fields inside of CPU
Also, clean up some of the cfg(debug) mess

benchmark report:

run_60_frames           time:   [110.61 ms 111.01 ms 111.42 ms]
                        change: [-7.1171% -6.5425% -5.9132%] (p = 0.00 < 0.05)
                        Performance has improved.


Former-commit-id: 9cb82e483c8a78632d0deae20adca9fc1843a76b
Former-commit-id: 6d9be5ddaf72f2b9c02063fa067f2ffbaea4fdb6
2020-11-24 00:54:18 +02:00
Michel Heily 586a5bf16c core: arm7tdmi: Refactor display->disass.
Also, move core::disass into core::arm7tdmi::disass


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Former-commit-id: 345ddaac674c78e77e62f106d7c0deda857fe5ed
2020-11-24 00:45:07 +02:00
Michel Heily 28a57a874a core: dma: Reduce logs
Former-commit-id: 6db019b583e195fcb6aedb134cf54482a6c72428
Former-commit-id: 9294c305aafac1d55f18f1bd5d2fb5c62db509c5
2020-11-06 06:26:00 -08:00
Michel Heily 7e2c9d040a [perf] core: gpu: Refactor to use unpacked mmio configuration during rendering
* Convert gpu bitfield!() registers to unpacked form, and defer pack/unpack to bus read/write operations


Former-commit-id: 26e7d7d62d6418ce7bcdb8e414cabe5ddb56333d
Former-commit-id: 716ddd9fe2b7b95b7613fc549a7bee406272478b
2020-11-06 06:26:00 -08:00
Michel Heily a413ebe891 [perf] core: arm7tdmi: inline arm7tdmi::Core::step function
run_60_frames           time:   [158.26 ms 160.84 ms 163.03 ms]
                        change: [-24.960% -18.808% -12.975%] (p = 0.00 < 0.05)
                        Performance has improved.

Wasn't expecting such an improvment tbh, but who am I to argue with results


Former-commit-id: a5ba74bffa26d962a232c0767a34a7d67ed8ccb4
Former-commit-id: 1b9b301ba9012e79e66822ac39af51df28c51fa4
2020-11-05 15:40:39 -08:00
Michel Heily 05b1ff10e3 [perf] core: gpu: optimize & clean finalize_scanline
Performance benchmark report improvement:
run_60_frames           time:   [176.85 ms 184.70 ms 191.47 ms]
                        change: [-11.727% -7.6991% -4.2923%] (p = 0.00 < 0.05)
                        Performance has improved.


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2020-11-05 15:40:39 -08:00
Michel Heily 22f544718a core: Add performance benchmark
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Former-commit-id: fd390604a7e01d9a67ffa0a70c5e9863f65fc9f8
2020-11-05 15:40:39 -08:00
Michel Heily ebd58261ba core: sound: Use correct variable when logging new sample rates
Former-commit-id: 6f5ff96dae03b2be061bcf06a6d701fda7ca15cb
Former-commit-id: 2934a02dfd36de2e794e8861df8f5035daab3165
2020-11-05 02:37:28 +02:00
Michel Heily efb1cdb4b6 core: Fix 8bit accesses to mgba log
Former-commit-id: 780e6b58b265ad5d586fe605f143e6c9d8b26c63
Former-commit-id: 5d2514c9a45d2f5c698272c9324575d7bddec4ac
2020-10-24 09:35:03 -07:00
Michel Heily fb32b9a671 core: Implement mGBA log support.
It's quite an handy way to log messages from ROMs, so I thought it'd be nice to add it.


Former-commit-id: 6869bdb58cfa883ac1ca6832f0bbeeab0edcf552
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2020-10-24 05:59:48 -07:00
Michel Heily b28fc3108f Bump arrayvec to 0.5.2
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Former-commit-id: 28de793611b50a9f6fc2933d6d92543a92cc2cb1
2020-10-24 05:59:48 -07:00
Michel Heily 40e306349c core: arm7tdmi: Force address alignment in memory accesses
Fixes #148


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2020-10-23 01:31:58 +03:00
Michel Heily aeecd98757 core: Fix debug read of OAM memory
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Former-commit-id: acda49ed0fffc481fe4b77fee1ef99b7038215df
2020-10-22 23:59:19 +03:00
Michel Heily 6b8f4e8f51 core: Implement open bus (Reading from unused memory)
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2020-10-18 09:41:35 -07:00
Michel Heily 8afb443354 core: dma; Calculate address adjustment once
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2020-10-18 08:33:37 -07:00
Michel Heily fc7ad01cc0 Forgot to restore scheduler pointers when restoring savestate :)
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2020-10-18 08:32:44 -07:00
Michel Heily b003dc950f core: Implement bios read protection when CPU is not executing from bios.
Fixes #109
Fixes #106
Fixes MegaMan email menu freezing and probably some more games


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2020-10-18 06:59:06 -07:00
Michel Heily 1ca261e5c7 core: Get rid of that BoxedMemory nonsense
Just directly impl Bus trait for Box<[u8]>


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Former-commit-id: 0c528165ed899fad14b1e25995fdfe8ae004da2a
2020-10-17 16:58:52 -07:00
Michel Heily 130a7608e7 [WIP] Gamepak unused addresses
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2020-10-17 06:53:28 -07:00
Michel Heily e14c5996d4 core: cartridge: Don't error when the checksum is invalid.
A lot of test ROMs i'm using don't bother to calculate the checksum :\


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2020-10-17 06:52:45 -07:00
Michel Heily a3546cbe07 Run cargo-fmt
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2020-10-17 06:36:02 -07:00
Michel Heily 44c9e2c875 core: dma: Count cycles passed in DMA transfers
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2020-10-17 06:36:02 -07:00
Michel Heily b6e2d55550 Everyday I'm ~~shuffeling~~ refactoring.
Some big refactors:
* improve scheduler performance by using a BinaryHeap
* refactor the scheduler API
* arm7tdmi
	* Change struct arm7tdmi::Core struct layout so frequently accesses fields would benefit from CPU cache
	* Simplify and cleanup cycle counting by implementing a MemoryInterface trait
	* Still not passing many cycle accuracy tests, but I believe it's because I don't have the prefetch buffer yet.
* Timer overflows are now scheduled
	* This fixes #111 and fixes #112
*


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2020-10-17 06:36:02 -07:00
Michel Heily 85db28dac6 core: debuggger: load symbols from elf files
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2020-10-17 06:36:02 -07:00
Michel Heily 3fa858f969 core: bus: Change read_x methods of Bus trait to take &mut self
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2020-10-17 06:36:02 -07:00