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Author SHA1 Message Date
Michel Heily be9499c76d Move cycle counting to CPU Core 
This isn't accurate, I'm probably missing something but at least it'll
make the instruction implementation more clean for now..


Former-commit-id: de24b15e1a51e1998207e5ea96fc8543f2553a26
 2019-07-05 13:08:07 +03:00
Michel Heily f8ebe26e5e Implement thumb format 13 
(NOT TESTED)


Former-commit-id: 160ee3a6c09a12cab53f69c94b385ea17666bd5f
 2019-07-05 03:46:04 +03:00
Michel Heily 5df9b6f317 Add thumb push-pop. 
Not tested, cycle modeling is crap


Former-commit-id: a5092dab79a1a660fc6c96a71f0908cc2054be27
 2019-07-05 03:28:02 +03:00
Michel Heily e66a8a9a3b Fix LR again :( 
Former-commit-id: 820315154ae58dcc29c4a8921094598f149b0255
 2019-07-05 03:27:23 +03:00
Michel Heily 2293300260 Add test for the bug fixed on e2a1303 
Former-commit-id: 98d0789aaf92a549cbe1b387461fd9acd4d773c0
 2019-07-04 02:06:41 +03:00
Michel Heily 702a08e30c Add many thumb instructions.. 
TODO add more tests for all the instructions I've got implemented so
far.
Also, I need to rewrite the whole "sysbus" module again because it's
crap and I keep refactoring it as I go.
I've added the "Dummy" because the bios for some reason tries to memzero
an unmapped region on the work ram (the thumb loop that ends at 0x126)


Former-commit-id: 67befd0935ee10df9ac8ceeaebd14f69767a7f16
 2019-07-04 01:56:50 +03:00
Michel Heily 984b17fa39 Fix arm mode STR insn 
Former-commit-id: 80903a9054e9b0dac07a5e2bb3cff7b0e722d438
 2019-07-04 01:56:11 +03:00
Michel Heily 923032f8cf REPL UI changes 
Former-commit-id: 6852b86541f967785dbffb6833fc2c11fa5dbef3
 2019-07-04 01:37:47 +03:00
Michel Heily 3541779fbf Fix LR when changing cpu modes 
Former-commit-id: 0ac911ee90758b9bffaafd459f1d9bca86d5064d
 2019-07-04 01:37:05 +03:00
Michel Heily 6a3d4358da Update .launch.json 
Former-commit-id: c922a1358c2a048d69c38e60734fc00ffa78a4a0
 2019-07-04 01:36:41 +03:00
= 28743702a1 Update waitstates for 256k work ram 
Former-commit-id: f5680c90e4ab4a9b29899cd5e0fe316d8227fc24
 2019-07-03 11:30:00 +03:00
MishMish c9df623d36 Update README.md 
Former-commit-id: 03b224b7de9735a1ed43dd7460fe5fa9ece147b4
 2019-07-03 02:23:36 +03:00
Michel Heily eaf972de93 Implement thumb format 6 (PC-Relative Load) and test it. 
Former-commit-id: ae161edb0c8968913d2ef72a14053c118c6f7692
 2019-07-03 02:15:16 +03:00
Michel Heily 58e1230e7a Model the cartidge. 
Former-commit-id: b51d2928631bfc438b9f1b15fafcaa9d90008179
 2019-07-03 01:40:08 +03:00
Michel Heily b82874809f Implement thumb format3 instruction and add a test for it. 
Former-commit-id: 8cf6664027dc3d5dbeb6d2ca3d089820baac2709
 2019-07-03 01:26:48 +03:00
Michel Heily 4011911cca Pass around "Bus" instead of "SysBus" 
Former-commit-id: c20dae7dd3ddcb3bd8f671a16fd67a241bd6c459
 2019-07-03 01:22:36 +03:00
Michel Heily 6f81c236a6 Mega Commit #2 - Add some thumb decoding and disassembly 
Former-commit-id: e3a89ac681a8d6f6f0bee85b32f64d181e11242f
 2019-07-03 00:03:35 +03:00
Michel Heily cbddeffd91 arm: Implement MSR_REG and fix some prefetching errors 
Former-commit-id: 177b8966159ed86472b0d4d031363df72d46807a
 2019-07-02 16:53:29 +03:00
Michel Heily 05fb40c17c debugger: Add Deref expression. 
i.e:
r5 = *r6
r5 = *(u8*)r6
r5 = *(u16*)0x08000000


Former-commit-id: 962dade8e3c0b9f291115285137cf51b0abde266
 2019-07-02 13:36:52 +03:00
Michel Heily 645e71ac40 Remove garbage file 
Former-commit-id: 906b8bc6f6b95ddc3565043ff4406a403e7ba08a
 2019-07-01 19:26:52 +03:00
Michel Heily 70179984d0 cpu: arm: Fix alu_add_update_carry function 
Woopsie


Former-commit-id: 2da74e4bfd4b59a2885519a99f4b2c3d83031ee2
 2019-07-01 19:25:42 +03:00
Michel Heily 2081b70ee2 cpu: arm: Fix R14 for branch with link instruction 
Former-commit-id: bc927d86e5a170b0e4568b4ceeb7832d23ad309c
 2019-07-01 19:24:52 +03:00
Michel Heily ea8c4f2a60 Refactor ArmInstructionFormat => ArmFormat 
Former-commit-id: 0ba6e1e6efedad55b2716b3f2ab5a2a629dd18a5
 2019-07-01 17:51:07 +03:00
Michel Heily 6b225d776d Implement all memory mappings. Reformat many files. 
Former-commit-id: c0a62b610e62d2db2a4daf4aeef40068820daa52
 2019-07-01 17:45:29 +03:00
Michel Heily 22c175d9cc Reorganize package structure 
Former-commit-id: d7ad26c07fc7063522fae061577f7ceece797ae5
 2019-07-01 16:15:42 +03:00
Michel Heily bd053354cb Implement LDR/STR (not tested) and add cycle counting 
Former-commit-id: ec9e6bfc2a94291e47d41ff7d839007879d3d694
 2019-06-30 16:59:37 +03:00
Michel Heily 98eee121fc Correct F flag behaviour when entrying an exception. 
Former-commit-id: b0ef6352d9f0c027657c6e5eeb615a131e9523d2
 2019-06-29 23:01:23 +03:00
Michel Heily 967ccca8dd Mega commit - model CPU pipelining. 
I except many bugs to arise..


Former-commit-id: bcc6ea57af803f783b0dd548b50956b3ccda2b1a
 2019-06-29 22:23:12 +03:00
Michel Heily 4c75970512 debugger: Detect error 
Former-commit-id: 1ea605eeab1a7b8e6645fe11d7b32c4c7dff0750
 2019-06-29 01:48:29 +03:00
Michel Heily 2238c7a72f Add demo gif to README.md 
Former-commit-id: 05ec55725c04cd4d4ca08471ea88b1b6b1b11e08
 2019-06-28 15:32:21 +03:00
Michel Heily c90448075f debugger: Fix breakpoint hit message 2019-06-28 15:07:29 +03:00
Michel Heily 64e0a02754 Add .vscode configuration for easy debugging 2019-06-28 15:05:18 +03:00
Michel Heily 3429b67c41 Fix test_decode_branch_backwards failing 2019-06-28 13:09:30 +03:00
Michel Heily 5245f0780c Update README.md 2019-06-28 13:05:48 +03:00
Michel Heily bd7fd472cf arm: Add tests for ldr/str 
And also test disassembling while at it..
 2019-06-28 12:36:19 +03:00
Michel Heily 7898bf61f3 arm: Fix bug when calculating 24bit branch offsets, and add a test for 
it.
 2019-06-28 12:01:49 +03:00
Michel Heily d11620e65b cpu: Add SWI instruction 
Also cleanup code, and add a test for swi decoding
 2019-06-28 11:46:36 +03:00
Michel Heily 1a0725f1a3 cpu: Model exceptions 2019-06-27 15:13:38 +03:00
Michel Heily fc6410b510 debugger: Make prompt bold 2019-06-27 15:04:15 +03:00
Michel Heily 1d766e95de cpu: Fix bug in psr mode bits 2019-06-27 15:03:44 +03:00
Michel Heily 948e0ccc25 Fix typo in .travis.yml 2019-06-27 13:16:00 +03:00
Michel Heily b9d1d38c2d debugger: Few improvements 2019-06-27 13:16:00 +03:00
Michel Heily 6552329310 cpu: Kinda implement data processing instructions 
When I say "Kinda", I mean that it is not tested well.
 2019-06-27 13:16:00 +03:00
Michel Heily 5808c03fcd cpu: Model Program Status Register. 2019-06-27 13:15:46 +03:00
Michel Heily 8a057ba159 debugger: Remember last command 2019-06-27 13:15:46 +03:00
Michel Heily 587ec3fc91 debugger: Add history to repl 2019-06-27 13:15:46 +03:00
Michel Heily f45a856835 Support assignment expressions for registers! 2019-06-27 13:15:46 +03:00
Michel Heily f1f33d8586 Improve debugger repl parsing. 
Add assignment expressions, add tests, and cleanup code.
 2019-06-27 13:15:46 +03:00
Michel Heily a70b92d5a4 Rename project 2019-06-27 13:15:46 +03:00
Michel Heily fc400ace5f Improve debug repl parsing :) 2019-06-27 13:15:46 +03:00