Commit graph

33 commits

Author SHA1 Message Date
Michel Heily
fb93ebb4ed feat/arm7tdmi_dispatch_table: Done!
Moved away from using lazy_static for this one since every access to a
lazy_static reference adds a runtime check, Currently using a build.rs script to generate a const table instead.

Worked out the ARM decoding issues, seems to run fine now.

Though the dynamic decoding for ARM is broken now since I had to change things in Data Processing and MSR instructions

TODO use `const fn` when it becomes stable


Former-commit-id: ba09748ff74a403c7016adcbe0ca553b591f6855
2020-04-07 02:31:13 +03:00
Michel Heily
a523a37d32 [WIP] Start working on arm7tdmi dispatch table.
Lookup tables are generally faster than matching in most architectures.
There is some trouble in decoding some arm data processing instructions
so this is non-default feature for now

* Crashes on armwrestler but many games seem to work


Former-commit-id: 3c06ea344ae0097947d8cd5bd05b1f882c7f743a
2020-04-07 02:30:22 +03:00
Michel Heily
f0aa671674 optimize/cpu: Pass Arm/Thumb Instruction and other large structs as references.
Also, get rid of unnecessary derive Copy.

Since the ArmInstruction (and Thumb) derived from Copy, the compiler
always saves them to the stack when they are passed by value to other
functions, thus making some unwanted performance overhead.

I removed the derive Copy, and also pass them as references. This
project has a lot of "derive Copy" everywhere, and I should take note if
this is happenning elsewhere aswell.


Former-commit-id: 2f94c6050fa26c5b777244bd26706d4e6e2f0dc9
2020-03-28 16:14:59 +03:00
Michel Heily
2af9249a6c optimize/arm: Force inlining.
This functions were not inlined by the optimizer


Former-commit-id: aa02a3f5e6d33f16c298bc655c8d3a244c2ef946
2020-03-28 16:14:59 +03:00
Michel Heily
c50ab1ecd8 feat: Add basic gdbserver feature
Initially I began implementing the gdb protocol on my own, but I then found a
nice work-in-progress crate on https://github.com/daniel5151/gdbstub
that suited my needs.


Former-commit-id: f77557cbbd8652c2ed05ac439efc1956d8e99729
2020-02-21 22:12:58 +02:00
Michel Heily
b03fe3567e Fix all warnings during build
Ran cargo-fix to automatically fix most of the build warnings,
Cleaned up dead code, and fix the rest manually


Former-commit-id: f35faba46b40eaf9c047efb8ab1e77ffa24d41b6
2020-02-14 14:21:45 +02:00
Michel Heily
0c2da2ae46 refactor: Refactor instruction decoding to panic instead of returning a Result
flamegraph shows too much time is being spent 'unwraping' decoded
instructions


Former-commit-id: e89072e6cf648e83f87d8c01891f50474246a36b
2020-02-14 13:05:14 +02:00
Michel Heily
32a20d2cbb ptimize: CPU Pipeline optimization part 3
Move reload_pipeline calls inside instructions.
This commit yeilds yet another 5% performance improvment.

The next step is to move `advance_pc` into the instructions themselves
and save the `match result` per executed instruction


Former-commit-id: 42193ffc48fda9943665e6a74e873186627a0b4a
2020-02-11 02:26:17 +02:00
Michel Heily
6beec306c2 optimize: CPU Pipeline optimization part 2
Optimize redundent pipeline stages
About 5% performance gain.

Also rustfmt..


Former-commit-id: 2f5fc95798e97eb963fea976866bbeaf637084b0
2020-02-11 02:26:17 +02:00
Michel Heily
1f79205f51 optimize: CPU Pipeline optimization part 1
In preperation for later optimization in the CPU pipeline
implementation, this commit refactors the arm/thumb exec functions to return a
CpuAction (Whether to advance the program counter or to flush the
pipeline)

Currently, a lot of host cycles are wasted in the arm7tdmi pipeline
Refill1 & Refill2 states. Optimizing these steps out would make the CPU
a bit faster.


Former-commit-id: 9be7966eaad22cceeb443fcc5823bbd945284027
2020-02-11 02:26:17 +02:00
Michel Heily
ae7bf63d3f arm7tdmi/optimize: Optimize and cleanup CPU, roughly about 10% fps improvement.
This commit removes the error handling (CpuResult<>) in order to reduce
overhead in the cpu implementation.
Also, some cleanup of warning messages.

Notice: this commit breaks '--feature debugger' for now

Former-commit-id: d4484047c3f5d509eff89cef7090aa88b07a8d17
2020-02-09 20:17:46 +02:00
Michel Heily
984cb2f0c4 chore: rust-fmt
Former-commit-id: 8bb31056864e64bcad6877f3c2c1000464cce82e
2020-02-07 17:16:52 +02:00
Michel Heily
40de6bf893 core: arm7tdmi: Align PC according to current ISA state
Former-commit-id: 049f01247f3fcc429f07e1761ceed25e749ce77e
2020-01-17 16:11:43 +02:00
Michel Heily
f4460b2740 feat/savestates: Implement save/load state API for GameBoyAdvance
Using serde & bincode encoding


Former-commit-id: f5e4c599497f6bdf3096fa99f8b2d6ce89278ef7
2020-01-16 20:18:32 +02:00
Michel Heily
36cf4e62ce core: arm7tdmi: optimization: split flush_pipeline to arm and thumb
Reduces an if check


Former-commit-id: 4380c54f86238ef8818356f4593f59277f055fa6
2020-01-11 16:12:54 +02:00
Michel Heily
b00fbfb38c gpu: refactor: Big refactor preparations
1) Decouple SysBus from Gpu
2) Split Gpu rendering function into separate modules
3) Cleanup


Former-commit-id: 0435ad1c9c1de72ed50769fabfea7c5f33b670e0
2019-12-29 23:44:34 +02:00
Michel Heily
fefeddbc40 Continue working on DMA sound.
Cleanup timer.rs
run cargo fmt
restore debugging continue&frame commands
Fix bug introduced in previous commit causing the bios animation to
hang


Former-commit-id: 188acaa1121503a97f2d3be816f6f57835e17fe1
2019-12-23 01:37:45 +02:00
Michel Heily
3c3129c73c Minor fixes
Fix LSR integer underflow.
Change SWI LR calculation


Former-commit-id: 6a298719e380c3a01f70c3b05d9f3507638398d5
2019-11-20 05:04:54 +02:00
Michel Heily
49ef59b8e9 fixup! Improve the debugger
Former-commit-id: 9ca33bd4f8273a6be66cec6a8218664a7aada376
2019-11-16 18:48:24 +02:00
Michel Heily
b9d0857acc Don't allow IRQs when pipeline is reloading
Former-commit-id: a51d3671dfabab422f2ad880b3cbe1bac65d442b
2019-11-16 18:17:53 +02:00
Michel Heily
b288625b9a Improve the debugger
- Add tracing of opcodes and potentially more stuff
- Add option to run a script file at the beginnig (I use it to redirect
traces to a file)
- Support breakpoints again


Former-commit-id: 4e988d6bc1a59456c96547f0320a6d9abedcae00
2019-11-16 18:17:53 +02:00
Michel Heily
7e98af80c2 Fixes to ALU, passing mGBA carry tests
Former-commit-id: 14a4293b2511c7c63a920e6344e89b209ca7c5ee
2019-11-16 18:17:53 +02:00
Michel Heily
1d088accb8 mGBA test suite now boots!
Fix tons of bug and reimplemented some of the core code.
Add a neat feature for debug builds:
When the cpu "swi 0x55" instruction, a breakpoint is triggered on the
host.


Former-commit-id: 959249df4374327d90b2503d7a45f8d5d27995a6
2019-11-12 18:22:00 +02:00
Michel Heily
c117cbe924 Make the debugger work again, but currently breakpoints are not supported.
Added memory write command and the ability to pause the debugger with Ctrl-C


Former-commit-id: 83d141fa191dadefb84f7c9de163631a69af8324
2019-11-12 18:22:00 +02:00
Michel Heily
3a1d5c10ce Fix many bugs, refactor many things..
Passing: Armwrestler, cpu_test by Dead_Body

Former-commit-id: 80d815d110c5341515dd01c476a0d7e25ecb66a8
2019-11-09 01:06:24 +02:00
Michel Heily
acd0e4f338 cpu: Refactor instructions to use explicit cycle counting.
The way cycles were counted up untill now was not accurate enough,
I've avoided doing so because the instruction implementation looks
bloated this way, but I've had problems with cycle accuracy with tonc's
timer demo.

This is not entirely correct though, and I'm 100% sure there are some
mistakes, but works good enough for now.


Former-commit-id: 748faaf99fe2f42925c0a2110192c6a01e5d27d4
2019-08-08 20:05:09 +03:00
Michel Heily
c7dd713605 The big ioregs refactoring.
This commit refactors the ioregs:
* Use bitfield crate to implement the GPU ioregs.
* IoRegs are stored in their own variables bindings (i.e, Gpu related ioregs are now fields of the Gpu struct)
  - This optimize performance quiet alot from my testings - since every scanline was accessing deseralizing ioregs from sysbus. (Getting constant 59fps now)
* For now, comment out DMA model

Also, cleaned the code up to eliminate rustc warnings.


Former-commit-id: 9077695c446ebd1a71783acfdd9819245aa02d7a
2019-08-03 00:24:15 +03:00
Michel Heily
1b5626a1a7 armwrestler-fix: Refactor barrel shifter and fix ALU carry flag, hopefully for good.
Passing most of armwrestler ALU tests (still have bugs in UMULL and
SMULL)


Former-commit-id: 3c57ca9b5360b5c9bba74b00a5bede5a8cc496af
2019-07-26 17:55:50 +03:00
Michel Heily
009e46f6d5 armwrestler-fix: Properly handle misaligned addresses LDR/LDRH/LDRSH
Former-commit-id: 742a7c2b8413fa9d45df1575a0b14b8d1ab697c4
2019-07-22 20:25:40 +03:00
Michel Heily
2fb6f3c884 Implement (psr / usr bank) transfers for LDM_STM
Former-commit-id: 140e6a6c75f65f08f645b1a0ff2ca7c065438ce4
2019-07-22 09:21:49 +03:00
Michel Heily
c0d437b1a1 Fix exceptions and dataprocess mode change
Former-commit-id: 5892131496904b621398212b9dfc077242fa9557
2019-07-22 01:16:48 +03:00
Michel Heily
7501adfd12 Implement thumb17 (Swi)
Former-commit-id: 62d7e14e9b84e74d9236e1f0a5e961ae805f861c
2019-07-22 01:15:58 +03:00
Michel Heily
53115a9a58 Refactor core functionality into a separate module
Former-commit-id: 5d55b9eb0b63ed7c61465b4e814782165caa5002
2019-07-20 16:46:00 +03:00
Renamed from src/arm7tdmi/cpu.rs (Browse further)