devraza/rustboyadvance-ng
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  • 19e4196384 Thumb 4 - Set flags if needed (For CMP) Michel Heily 2019-07-09 01:28:14 +0300
  • 0bdf4993ee thumb: Word align PC when jumping to Arm code Michel Heily 2019-07-09 01:27:23 +0300
  • 6ddb136852 alu: Also fix carry detection for unsigned addition Michel Heily 2019-07-09 00:39:35 +0300
  • 6c0df33597 Finally got the barrel shifter right? Michel Heily 2019-07-08 21:58:30 +0300
  • 2817db4e1c alu: Fix carry detection for subtraction Michel Heily 2019-07-09 00:30:23 +0300
  • 1bacb927af Fix ROR with amount > 32 Michel Heily 2019-07-08 21:03:47 +0300
  • 9421281381 Fix THUMB 1 Michel Heily 2019-07-08 20:58:22 +0300
  • f7b2b48e5d Refactor ALU code into its own module, and fix things. Michel Heily 2019-07-08 19:56:12 +0300
  • ecdd6e0ed4 thumb: Fix ALU ops for barrel shifter opcodes Michel Heily 2019-07-08 01:47:41 +0300
  • 163d8bda59 Fix not flushing the pipeline for "mov pc, reg" instructions Michel Heily 2019-07-08 00:58:09 +0300
  • 863838a4a4 Force R15 alignment via cpu.set_reg Michel Heily 2019-07-08 00:57:18 +0300
  • 7e7d2c5208 thumb: Fix misimplementation of THUMB 12 :( Michel Heily 2019-07-08 00:49:03 +0300
  • 6eab76d52f Impose a minimum length of 4MB for the gamepak memory Michel Heily 2019-07-07 23:33:47 +0300
  • d36da30618 arm: Impl LDR_STR_HS Michel Heily 2019-07-07 23:10:17 +0300
  • 45f3bd6264 arm: Fix STR use of R15 as the base register (Rd) Michel Heily 2019-07-07 22:57:21 +0300
  • c92bde54a1 Begin modeling DMA Michel Heily 2019-07-07 01:33:54 +0300
  • c2685c14d7 Impl more thumb, Fix more things, the usual Michel Heily 2019-07-06 23:38:08 +0300
  • 6dd48c6238 Add option to skip bios code so I can start checking out test roms Michel Heily 2019-07-06 19:26:51 +0300
  • 36dba78c55 More fixes Michel Heily 2019-07-06 18:48:22 +0300
  • 8dc169d25d fix: bug in some ALU opcodes Michel Heily 2019-07-06 18:47:42 +0300
  • efb5d361d6 Add PaletteView command for the debugger. Michel Heily 2019-07-06 16:04:43 +0300
  • 3cc84b1b03 Model many things Michel Heily 2019-07-06 15:53:36 +0300
  • d1ef35646f Impl Thumb LdrStrImmOffset Michel Heily 2019-07-06 15:51:58 +0300
  • 600bebc9d2 Partially Impl Arm LDM_STM (give me a break) Michel Heily 2019-07-05 18:38:20 +0300
  • 4da863da9b Fix carry flag on barrel shifter ops Michel Heily 2019-07-05 18:31:08 +0300
  • 638e449421 Impl Thumb 18 (Branch) Michel Heily 2019-07-05 16:21:24 +0300
  • 74329c2a0b Never leave unfinished work.. Michel Heily 2019-07-05 16:10:21 +0300
  • 0c50209735 Fix wrong calculation of conditional branch offset in Thumb mode Michel Heily 2019-07-05 16:01:16 +0300
  • 37117257a6 Impl Thumb 10 (load store halfword) Michel Heily 2019-07-05 15:50:14 +0300
  • d4b6952411 Impl Thumb 19, fix warnings and rustfmt Michel Heily 2019-07-05 15:34:52 +0300
  • fb0d3acb14 Impl Thumb Format 1 untested Michel Heily 2019-07-05 14:09:04 +0300
  • 058760d7e4 Impl thumb Format4 Michel Heily 2019-07-05 13:58:26 +0300
  • 01290f6a28 Impl Thumb LdrStrSp Michel Heily 2019-07-05 13:20:19 +0300
  • be9499c76d Move cycle counting to CPU Core Michel Heily 2019-07-05 13:07:07 +0300
  • f8ebe26e5e Implement thumb format 13 (NOT TESTED) Michel Heily 2019-07-05 03:46:04 +0300
  • 5df9b6f317 Add thumb push-pop. Michel Heily 2019-07-05 03:28:02 +0300
  • e66a8a9a3b Fix LR again :( Michel Heily 2019-07-05 03:27:23 +0300
  • 2293300260 Add test for the bug fixed on e2a1303 Michel Heily 2019-07-04 02:06:41 +0300
  • 702a08e30c Add many thumb instructions.. Michel Heily 2019-07-04 01:56:50 +0300
  • 984b17fa39 Fix arm mode STR insn Michel Heily 2019-07-04 01:56:11 +0300
  • 923032f8cf REPL UI changes Michel Heily 2019-07-04 01:37:47 +0300
  • 3541779fbf Fix LR when changing cpu modes Michel Heily 2019-07-04 01:37:05 +0300
  • 6a3d4358da Update .launch.json Michel Heily 2019-07-04 01:36:41 +0300
  • 28743702a1 Update waitstates for 256k work ram = 2019-07-03 11:30:00 +0300
  • c9df623d36 Update README.md MishMish 2019-07-03 02:23:36 +0300
  • eaf972de93 Implement thumb format 6 (PC-Relative Load) and test it. Michel Heily 2019-07-03 02:15:16 +0300
  • 58e1230e7a Model the cartidge. Michel Heily 2019-07-03 01:40:08 +0300
  • b82874809f Implement thumb format3 instruction and add a test for it. Michel Heily 2019-07-03 01:26:48 +0300
  • 4011911cca Pass around "Bus" instead of "SysBus" Michel Heily 2019-07-03 01:22:36 +0300
  • 6f81c236a6 Mega Commit #2 - Add some thumb decoding and disassembly Michel Heily 2019-07-02 16:57:35 +0300
  • cbddeffd91 arm: Implement MSR_REG and fix some prefetching errors Michel Heily 2019-07-02 16:42:55 +0300
  • 05fb40c17c debugger: Add Deref expression. Michel Heily 2019-07-02 13:31:02 +0300
  • 645e71ac40 Remove garbage file Michel Heily 2019-07-01 19:26:52 +0300
  • 70179984d0 cpu: arm: Fix alu_add_update_carry function Michel Heily 2019-07-01 19:25:42 +0300
  • 2081b70ee2 cpu: arm: Fix R14 for branch with link instruction Michel Heily 2019-07-01 19:24:52 +0300
  • ea8c4f2a60 Refactor ArmInstructionFormat => ArmFormat Michel Heily 2019-07-01 17:51:07 +0300
  • 6b225d776d Implement all memory mappings. Reformat many files. Michel Heily 2019-07-01 17:45:29 +0300
  • 22c175d9cc Reorganize package structure Michel Heily 2019-06-30 22:31:16 +0300
  • bd053354cb Implement LDR/STR (not tested) and add cycle counting Michel Heily 2019-06-30 16:59:19 +0300
  • 98eee121fc Correct F flag behaviour when entrying an exception. Michel Heily 2019-06-29 23:01:23 +0300
  • 967ccca8dd Mega commit - model CPU pipelining. Michel Heily 2019-06-29 01:52:10 +0300
  • 4c75970512 debugger: Detect error Michel Heily 2019-06-29 01:48:29 +0300
  • 2238c7a72f Add demo gif to README.md Michel Heily 2019-06-28 15:32:21 +0300
  • c90448075f debugger: Fix breakpoint hit message Michel Heily 2019-06-28 15:06:38 +0300
  • 64e0a02754 Add .vscode configuration for easy debugging Michel Heily 2019-06-28 14:58:17 +0300
  • 3429b67c41 Fix test_decode_branch_backwards failing Michel Heily 2019-06-28 13:09:30 +0300
  • 5245f0780c Update README.md Michel Heily 2019-06-28 13:05:48 +0300
  • bd7fd472cf arm: Add tests for ldr/str Michel Heily 2019-06-28 12:36:19 +0300
  • 7898bf61f3 arm: Fix bug when calculating 24bit branch offsets, and add a test for it. Michel Heily 2019-06-28 12:01:49 +0300
  • d11620e65b cpu: Add SWI instruction Michel Heily 2019-06-28 11:46:36 +0300
  • 1a0725f1a3 cpu: Model exceptions Michel Heily 2019-06-27 15:13:38 +0300
  • fc6410b510 debugger: Make prompt bold Michel Heily 2019-06-27 15:04:15 +0300
  • 1d766e95de cpu: Fix bug in psr mode bits Michel Heily 2019-06-27 15:03:44 +0300
  • 948e0ccc25 Fix typo in .travis.yml Michel Heily 2019-06-27 13:01:46 +0300
  • b9d1d38c2d debugger: Few improvements Michel Heily 2019-06-27 12:55:28 +0300
  • 6552329310 cpu: Kinda implement data processing instructions Michel Heily 2019-06-27 00:48:43 +0300
  • 5808c03fcd cpu: Model Program Status Register. Michel Heily 2019-06-27 00:45:53 +0300
  • 8a057ba159 debugger: Remember last command Michel Heily 2019-06-27 00:41:54 +0300
  • 587ec3fc91 debugger: Add history to repl Michel Heily 2019-06-27 00:22:41 +0300
  • f45a856835 Support assignment expressions for registers! Michel Heily 2019-06-26 16:34:42 +0300
  • f1f33d8586 Improve debugger repl parsing. Michel Heily 2019-06-26 12:05:53 +0300
  • a70b92d5a4 Rename project Michel Heily 2019-06-26 10:23:16 +0300
  • fc400ace5f Improve debug repl parsing :) Michel Heily 2019-06-25 21:31:45 +0300
  • e5d93f689f Work.. Michel Heily 2019-06-25 13:28:02 +0300
  • 22a915ec85 Add continue command Michel Heily 2019-06-25 05:35:52 +0300
  • 9921f1c974 Add info and reset commands Michel Heily 2019-06-25 05:16:14 +0300
  • fc28d89097 Implement a few debugger commands Michel Heily 2019-06-25 04:59:18 +0300
  • 107e34aca1 Start debugger repl Michel Heily 2019-06-25 03:07:47 +0300
  • 9330c53957 Start modeling CPU Michel Heily 2019-06-25 02:10:09 +0300
  • addea1efa0 Merge both packages Michel Heily 2019-06-24 22:02:00 +0300
  • 094cbb5f29 Refactor disassembler binary into arm7tdmi package Michel Heily 2019-06-24 21:45:25 +0300
  • 5a5efae4c0 Refactor disassembler => disass Michel Heily 2019-06-24 20:53:56 +0300
  • dffb739d47 Finish disassembler for now Michel Heily 2019-06-24 20:20:08 +0300
  • 377f350e12 Start arm disassembler Michel Heily 2019-06-23 02:57:14 +0300
  • f18ec05c17 Create .travis.yml Michel Heily 2019-06-21 13:14:12 +0300
  • 4a67ecd1bc Create LICENSE MishMish 2019-06-21 13:11:03 +0300
  • 8324c1ed50 Initial commit Michel Heily 2019-06-21 13:08:18 +0300