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Author SHA1 Message Date
Michel Heily 1d2d950729 Fix IoRegs::write_8 
Former-commit-id: 9877e7f42fefafb71dd319287e01d55926d4d12c
 2019-08-24 00:33:01 +03:00
Michel Heily f40ee148ea Add sdl2 key mappings 
Former-commit-id: 9b3aa941ffca9a679d9ce70ca43d6396d4dfe5ff
 2019-08-23 22:47:12 +03:00
Michel Heily 4a72a1035f Fix Rgb15::is_transparent bug 
Former-commit-id: f12729b993ec9bef94a58a4d48982c7d3939c45b
 2019-08-17 21:27:36 +03:00
Michel Heily 639993edd7 Add blending and mosaic SFX, and cleanup code. 
Former-commit-id: b9f0ccaf1820da61f49ebeb2af5beff5cccd722f
 2019-08-13 22:15:36 +03:00
Michel Heily c4b24fde02 Refactor GPU registers wrappers to a separate module 
Former-commit-id: 3e7c6326232cd761674061ceed758a56412da17f
 2019-08-11 22:35:32 +03:00
Michel Heily 52ef793759 Move gpu module to a separate folder, to allow for later cleanup. 
Also, get rid of "render" command


Former-commit-id: 7dd004f3ff8f55686665adead497ebae4f873379
 2019-08-11 22:28:52 +03:00
Michel Heily edf2efcce5 Fix panic if debugger histfile does not exist 
Former-commit-id: a355a783b4d513dd3c65ef41de6a7604853a7b0f
 2019-08-11 21:50:44 +03:00
Michel Heily 9064ae9cf8 Fix bug in IoRegs::write_32 
Former-commit-id: a2c5b57a0e7da2fa0f080d70acd77b8643bc4742
 2019-08-11 21:50:44 +03:00
Michel Heily 3f6a52cae6 Add sdl2 backend 
Currently has bad performance


Former-commit-id: 384ef6b5cd7b1e1baeb6adfbc0b299b0d07d7a5d
 2019-08-10 18:14:59 +03:00
Michel Heily acd0e4f338 cpu: Refactor instructions to use explicit cycle counting. 
The way cycles were counted up untill now was not accurate enough,
I've avoided doing so because the instruction implementation looks
bloated this way, but I've had problems with cycle accuracy with tonc's
timer demo.

This is not entirely correct though, and I'm 100% sure there are some
mistakes, but works good enough for now.


Former-commit-id: 748faaf99fe2f42925c0a2110192c6a01e5d27d4
 2019-08-08 20:05:09 +03:00
Michel Heily d86cc87c79 Add WAITCNT, and refactor cycle calculation 
Former-commit-id: e1ee5c9ce1f1db549fddd80907467da51e63b676
 2019-08-07 09:50:33 +03:00
Michel Heily fe071bf1ec Fix timer bugs 
Former-commit-id: 9839368895dca306b66a095ab0b9386c77bd2c12
 2019-08-07 09:45:10 +03:00
Michel Heily c72bbb96fd [WIP] Timers 
Seems to work, but the cycle's are not accurate so they run slowly


Former-commit-id: a0b80acb4b68ed64caa535a0ec9f75a081d3aed4
 2019-08-05 09:53:41 +03:00
Michel Heily c7dd713605 The big ioregs refactoring. 
This commit refactors the ioregs:
* Use bitfield crate to implement the GPU ioregs.
* IoRegs are stored in their own variables bindings (i.e, Gpu related ioregs are now fields of the Gpu struct)
  - This optimize performance quiet alot from my testings - since every scanline was accessing deseralizing ioregs from sysbus. (Getting constant 59fps now)
* For now, comment out DMA model

Also, cleaned the code up to eliminate rustc warnings.


Former-commit-id: 9077695c446ebd1a71783acfdd9819245aa02d7a
 2019-08-03 00:24:15 +03:00
Michel Heily 9f0df9af06 optimization: Optimize VRAM accesses from within the gpu. 
Not going through the memory mapping anymore.

Also, this commit wraps the gpu pixeldata with a struct


Former-commit-id: d7b706d9de61bac7909e10d6bbe092968e6acc9f
 2019-08-02 18:04:35 +03:00
Michel Heily eb2a1a02fe Implement background scrolling! 
tonc's brin_demo.gba now works as intended :)


Former-commit-id: 596c063c5968534f42e42f52203c85262b9c6fa2
 2019-07-31 00:52:46 +03:00
Michel Heily f862209911 Support axis flip for tiles 
Former-commit-id: daefb380ab2dfcee600297690dcc0c7c1a37f911
 2019-07-29 09:46:12 +03:00
Michel Heily 90edebbe82 Align to halfword for thumb branch long instructions 
Former-commit-id: f75e4baf003dcb7c535db3692383cc95575dfd81
 2019-07-29 01:55:16 +03:00
Michel Heily e962150aaf Start working on Interrupts. 
it kinda works now, but needs testing.


Former-commit-id: 8510314cce248a737d492d935cf5b48f86d920ed
 2019-07-29 01:28:22 +03:00
Michel Heily 66a484e3ae Fix mode0 calculation of tile map entries. 
tonc's hello.gba demo now works correctly :)


Former-commit-id: ead3a01e810f69503abbe8bddd0853433862549b
 2019-07-27 23:28:00 +03:00
Michel Heily f39095a03b Fix thumb conditional branch offset 
Former-commit-id: b42f233b7f2ca5d427b0e36860a305f7e1a26a1d
 2019-07-27 21:30:27 +03:00
Michel Heily df48f307f0 armwrestler-fix: Fix post indexed LDR_STR when rd==rn 
Former-commit-id: b886c969c2d570fbb831eeeddc0f65ad575cfccb
 2019-07-27 21:28:43 +03:00
Michel Heily 477b4f45fd Fix thumb MUL not setting the flags 
Former-commit-id: b43e35a7fa2894fcc5cef7eeae9d74123e40219b
 2019-07-27 20:25:59 +03:00
Michel Heily 44426b5f0e Impl arm SWP 
Also ran some rustfmt


Former-commit-id: 30480e79d7f2926d5a5f15db20427179a672a78c
 2019-07-27 20:20:58 +03:00
Michel Heily e06c77b6fd armwrestler-fix: Fix MULL_MLAL instructions 
Also fix disassembly for MULL_MLAL


Former-commit-id: f535b2db7edb5d056160699436dbeb0c15e61388
 2019-07-27 18:57:20 +03:00
Michel Heily 7429236471 Fix mistake in UMLAL 
Former-commit-id: 6fe9bdf5471b71b58dcf9ee9ffa03c41b24e6301
 2019-07-26 17:55:50 +03:00
Michel Heily 1b5626a1a7 armwrestler-fix: Refactor barrel shifter and fix ALU carry flag, hopefully for good. 
Passing most of armwrestler ALU tests (still have bugs in UMULL and
SMULL)


Former-commit-id: 3c57ca9b5360b5c9bba74b00a5bede5a8cc496af
 2019-07-26 17:55:50 +03:00
Michel Heily 24483456ed armwrestler-fix: Fix writeback for LDR where rd==rn 
Instead of returning an Err, the writeback should just be disabled.


Former-commit-id: 91636a4eeaf76d0dbd11d250202671fcf8aaa4e6
 2019-07-22 20:33:31 +03:00
Michel Heily 009e46f6d5 armwrestler-fix: Properly handle misaligned addresses LDR/LDRH/LDRSH 
Former-commit-id: 742a7c2b8413fa9d45df1575a0b14b8d1ab697c4
 2019-07-22 20:25:40 +03:00
Michel Heily 2a66e525b1 Fix thumb disassembly of LDMIA/STMIA 
Former-commit-id: b04b07f181fff82869503671dd0f500a6c3e5fb1
 2019-07-22 09:31:35 +03:00
Michel Heily 2fb6f3c884 Implement (psr / usr bank) transfers for LDM_STM 
Former-commit-id: 140e6a6c75f65f08f645b1a0ff2ca7c065438ce4
 2019-07-22 09:21:49 +03:00
Michel Heily 0b5902c52e Implement special MRS 
Former-commit-id: 1af358887ef71344987f72d65612095c72565f43
 2019-07-22 09:21:45 +03:00
Michel Heily c0d437b1a1 Fix exceptions and dataprocess mode change 
Former-commit-id: 5892131496904b621398212b9dfc077242fa9557
 2019-07-22 01:16:48 +03:00
Michel Heily 7501adfd12 Implement thumb17 (Swi) 
Former-commit-id: 62d7e14e9b84e74d9236e1f0a5e961ae805f861c
 2019-07-22 01:15:58 +03:00
Michel Heily eea26d2393 thumb: Change ordering when decoding thumb instruction. 
This fixes a bug where "swi" instructions are decoded as conditional
branches.

The order really matters here, because Swi instructions are actually
conditional branch with illegal condition code.


Former-commit-id: 0024a8b53386a510dd321c157391c99a2af29223
 2019-07-22 00:25:26 +03:00
Michel Heily 387e26fad9 Add support for BGMode3 (tonc first.gba example now working) 
Former-commit-id: 52ac773ee2c3542ff3b046c3ea33fde02e804492
 2019-07-22 00:09:44 +03:00
Michel Heily 7e9c0e31da Add minifb backend - Armwrestler now plays ! 
Former-commit-id: d72ea9139e04624322cf3bc4a8ab330f6bb133a4
 2019-07-20 23:02:18 +03:00
Michel Heily 61e1f055f1 Model the keypad 
Former-commit-id: 4f38fa754e3ee809a7386351297decb2d7f1451f
 2019-07-20 22:58:29 +03:00
Michel Heily 53115a9a58 Refactor core functionality into a separate module 
Former-commit-id: 5d55b9eb0b63ed7c61465b4e814782165caa5002
 2019-07-20 16:46:00 +03:00
Michel Heily 0f73abaf98 Optimize instructions with "register lists" (LDM_STM) 
These instruction (probably) allocated a vector each time.


Former-commit-id: 66f724e21e1e5d667d19c1f21d2cc4fa3944faac
 2019-07-20 16:07:19 +03:00
Michel Heily 7119ba2451 Cpu: Rewrite pipeline code. 
Pipeline code was unreadable up until now, this also fixes a bug:

* Some roms have illegal instructions right after branch instructions, and
the cpu would error trying to decode them because of pipelining.


Former-commit-id: e3201c7b0d2adfc772231a3e2d5909f43c17b50f
 2019-07-20 16:03:37 +03:00
Michel Heily 1f074e20ad Refactor lcd -> gpu 
Former-commit-id: c12be139770922bac55490c76348f5406fc00f07
 2019-07-16 01:21:11 +03:00
Michel Heily 876cdfdcb3 Implement MODE4 rendering, ArmWrestler renders now! 
Former-commit-id: 4910a63b454ae9309abc0aa584a7d0bc96143538
 2019-07-15 20:49:47 +03:00
Michel Heily 1084be52b8 WIP mode0 rendering 
Former-commit-id: 6bce375f9373bbddf4522da5ecc2ea3584373847
 2019-07-15 19:23:16 +03:00
Michel Heily 9d8272b895 Fix wrong use of rust ranges in the lcd.rs module 
Former-commit-id: 73d588299baed7f5206b904f40ecf4a4e5283ef6
 2019-07-15 19:09:41 +03:00
Michel Heily a4925b7233 Fix SP values for "--skip-bios" 
Former-commit-id: d89d3c9c6b5d062137442df4017d59dea047270f
 2019-07-15 07:31:29 +03:00
Michel Heily 0500d33cb7 Refactor bus interface 
Former-commit-id: f325cda23f5e9946b367456d82ba71bb92bdd46e
 2019-07-15 07:30:52 +03:00
Michel Heily f08da850c7 thumb: Fix overflowing multiplication 
Former-commit-id: 5dbd45f9fd3811726aad9c32444f0dcf42d0b8be
 2019-07-13 23:33:37 +03:00
Michel Heily ab8c067616 Flush pipelines when entering an exception 
Former-commit-id: c00754b8156ecac66cc0a72f6a7c73ee700448f0
 2019-07-13 23:33:10 +03:00
Michel Heily fb5229705b Refactor and fix arm condition check 
Former-commit-id: 132c14fc56a21426263971e2d544ff10f072fea1
 2019-07-13 23:32:43 +03:00
Michel Heily 1747addcd3 Start modeling the Lcd Display 
Former-commit-id: 544f185c6f9eead870032170292b1cc8afc724bf
 2019-07-11 18:17:28 +03:00
Michel Heily 95f45e55a9 arm: Impl MULL_MLAL and fix writeback for post-index memory transfers 
Also some minor fixes and formatting


Former-commit-id: 4929b28cbb4eeeed5acfbdcdd19392ffa3bb0f37
 2019-07-11 18:10:58 +03:00
Michel Heily 4763f79abf arm: Impl MLA 
Former-commit-id: fe2c836bd09af165381537445dd288ca7bac24ce
 2019-07-11 00:02:39 +03:00
Michel Heily 5bc4c79d6e arm: Implement MRS 
Former-commit-id: 8c1528b2bcd08096f929c4ee940f1a1f5eac2911
 2019-07-10 23:54:45 +03:00
Michel Heily 5f625b2209 Add special case for MSR immediate 
Former-commit-id: f9fabb3c0d7c05243866b712096c2c82cf41672d
 2019-07-10 23:48:14 +03:00
Michel Heily a9bf2d25e0 arm: Implement Arm MSR_FLAGS 
Former-commit-id: 64d2cf255304ecca02dadc55266d22bc1f92bb4c
 2019-07-10 22:35:40 +03:00
Michel Heily 4c3379615a Fix bug in RRX (defined "old_carry" after changing it >< ) 
Former-commit-id: b890d40bb57da1cc6b63d6436bc8f346131fa5bc
 2019-07-10 22:35:40 +03:00
Michel Heily 50086a8715 Fix word alignment for arm BX 
Former-commit-id: 9223259793cd8ecccb02b40c428d32315c632bff
 2019-07-10 22:35:40 +03:00
Michel Heily 2864f83681 Arm: Partially implement MUL 
Former-commit-id: 3b37f5cbe327e15be4cee56572c2230dbda48082
 2019-07-10 22:35:40 +03:00
Tamir 543161d6b8 Fix cli help lines to all follow the same structure 
Help lines all start with a capital letter and don't end with a dot


Former-commit-id: 31e65514d15540538e2de528810957e16c8b5090
 2019-07-10 12:59:48 +03:00
Michel Heily 92f65794d8 Fix writeback for Thumb LdmStm 
Former-commit-id: 00a15dc99716290da7b260b261090454d621ce8a
 2019-07-09 02:20:32 +03:00
Michel Heily 65de0c4e9d Thumb 4 - Take care of "neg" case. 
I overlooked it :/


Former-commit-id: 360eb755bcf343cddd98807e9faeff007c94cf64
 2019-07-09 01:30:24 +03:00
Michel Heily 34233fa654 alu: Fix bug in SBC and RSC ops 
Former-commit-id: 1cb23d6280e1816395c46a7571dd9f48df870202
 2019-07-09 01:29:34 +03:00
Michel Heily 19e4196384 Thumb 4 - Set flags if needed (For CMP) 
Former-commit-id: 4f5bc97375c8aa45036b025a3420331a8137da17
 2019-07-09 01:28:14 +03:00
Michel Heily 0bdf4993ee thumb: Word align PC when jumping to Arm code 
Former-commit-id: 55fa28246c45a6bd807c53ce8bf0bb5865d36564
 2019-07-09 01:27:23 +03:00
Michel Heily 6ddb136852 alu: Also fix carry detection for unsigned addition 
Former-commit-id: d405f885e2b54c23aef5faab86cc1da681bd05ec
 2019-07-09 00:40:52 +03:00
Michel Heily 6c0df33597 Finally got the barrel shifter right? 
The barrel shifter sure has lots of edge cases, need to implement tests ASAP


Former-commit-id: 989fc4477f610603154404d0ed4335619ebd6345
 2019-07-09 00:33:53 +03:00
Michel Heily 2817db4e1c alu: Fix carry detection for subtraction 
Former-commit-id: c9d8612f72ce4a002ea33446209bd7e6da0eb5aa
 2019-07-09 00:33:53 +03:00
Michel Heily 1bacb927af Fix ROR with amount > 32 
Former-commit-id: 8f88de3c55c0e452266c40944ff920175b83627e
 2019-07-08 21:03:47 +03:00
Michel Heily 9421281381 Fix THUMB 1 
I didn't send this through the ALU :/


Former-commit-id: 40b4d23dcd769496e9dcd47bbf8d472b91e6a7bf
 2019-07-08 20:58:22 +03:00
Michel Heily f7b2b48e5d Refactor ALU code into its own module, and fix things. 
* Fix overflow flag being ignored
* Fix barrel shifter misimplementations
* Rustfmt fixes


Former-commit-id: a14d50372f7850a04b204accf4e5d8b924e4b48e
 2019-07-08 20:57:58 +03:00
Michel Heily ecdd6e0ed4 thumb: Fix ALU ops for barrel shifter opcodes 
I kinda missed these when I read the manual ><


Former-commit-id: 7d6c21b6c3b46bf065a177c1c7f7a7a1baa6b8fa
 2019-07-08 01:47:41 +03:00
Michel Heily 163d8bda59 Fix not flushing the pipeline for "mov pc, reg" instructions 
Former-commit-id: 66136ef70b8f48d5e9f4c10b65f1e2fbd3dd3ea1
 2019-07-08 00:58:09 +03:00
Michel Heily 863838a4a4 Force R15 alignment via cpu.set_reg 
I've encounted many bugs with instructions that write PC but don't align
it.


Former-commit-id: b6a234564729f83c0b5e8adfa293227299aad4ac
 2019-07-08 00:57:18 +03:00
Michel Heily 7e7d2c5208 thumb: Fix misimplementation of THUMB 12 :( 
And this kids, is why you don't ever assume what an instruction does
without reading the manual.
Also, I called the ThumbFormat enum variant "LdrAddress", so I went
ahead and implemented as an ldr_str :/


Former-commit-id: f13833d16fba07565a0aba9d247d9754dbfc3d39
 2019-07-08 00:49:03 +03:00
Michel Heily 6eab76d52f Impose a minimum length of 4MB for the gamepak memory 
Former-commit-id: 08e66bff0bc39968e572b941da84c155a45f31c8
 2019-07-07 23:33:47 +03:00
Michel Heily d36da30618 arm: Impl LDR_STR_HS 
Former-commit-id: 2baa0f2fb8cf855cb4626fbb1937e17f4e7d3035
 2019-07-07 23:10:17 +03:00
Michel Heily 45f3bd6264 arm: Fix STR use of R15 as the base register (Rd) 
Former-commit-id: 696733731a9996ebb90b7d4acf3341facc1ed228
 2019-07-07 22:57:21 +03:00
Michel Heily c92bde54a1 Begin modeling DMA 
Former-commit-id: 83ab601e70666f76ed3ebfb22340c6b1868af3ac
 2019-07-07 01:47:51 +03:00
Michel Heily c2685c14d7 Impl more thumb, Fix more things, the usual 
Former-commit-id: 02f1898bfd8dd50519f103bb367e358fc55c46e7
 2019-07-06 23:38:08 +03:00
Michel Heily 6dd48c6238 Add option to skip bios code so I can start checking out test roms 
Former-commit-id: b78c8d9807ba3097d641a57ec7fcd500b32b4d96
 2019-07-06 19:26:51 +03:00
Michel Heily 36dba78c55 More fixes 
Former-commit-id: 897cbc0fb9c12469606c48ee8a02d35bf82c2ae5
 2019-07-06 18:48:22 +03:00
Michel Heily 8dc169d25d fix: bug in some ALU opcodes 
Former-commit-id: 7e05a11a709ad7f834916afa82ec5460068363f9
 2019-07-06 18:47:42 +03:00
Michel Heily efb5d361d6 Add PaletteView command for the debugger. 
Former-commit-id: c4e0250eea700cfbcbb9f904cde7b6bc055d3e05
 2019-07-06 16:04:43 +03:00
Michel Heily 3cc84b1b03 Model many things 
Former-commit-id: b87fa2b16b395f497cf217ea043e68404ab2f65e
 2019-07-06 15:54:07 +03:00
Michel Heily d1ef35646f Impl Thumb LdrStrImmOffset 
Former-commit-id: 17d6f4ae1cb5f68b9fccf35536a6346e88326e77
 2019-07-06 15:51:58 +03:00
Michel Heily 600bebc9d2 Partially Impl Arm LDM_STM (give me a break) 
Manually testing seems to work, too lazy to write any tests now,
Will do it after all instructions are complete, buggy or not.


Former-commit-id: 0f36c81d6451c706408dd3c4815bfb3abea1ff44
 2019-07-05 18:39:10 +03:00
Michel Heily 4da863da9b Fix carry flag on barrel shifter ops 
Former-commit-id: 31cf2166d97fcdcca0dd9c59591f5e28b5b5f6cc
 2019-07-05 18:31:08 +03:00
Michel Heily 638e449421 Impl Thumb 18 (Branch) 
Former-commit-id: 152dab739a1fa1b9d324084fc810b8540af9c3d7
 2019-07-05 16:21:24 +03:00
Michel Heily 74329c2a0b Never leave unfinished work.. 
Former-commit-id: 91acecdaf3ec7f9de892bd9f712e3cf521e08beb
 2019-07-05 16:10:21 +03:00
Michel Heily 0c50209735 Fix wrong calculation of conditional branch offset in Thumb mode 
Former-commit-id: 4cc28b13b19b2bf45e2b0e34d9a9dc0f83f82b01
 2019-07-05 16:01:16 +03:00
Michel Heily 37117257a6 Impl Thumb 10 (load store halfword) 
Former-commit-id: 0d5e88f200613b6df2b999ecbb855ce480e73322
 2019-07-05 15:50:14 +03:00
Michel Heily d4b6952411 Impl Thumb 19, fix warnings and rustfmt 
Former-commit-id: 8690aa25b1aa343b344776716b6213596bd1459a
 2019-07-05 15:34:52 +03:00
Michel Heily fb0d3acb14 Impl Thumb Format 1 untested 
Former-commit-id: e80617fd415ba951310a42c79b6ca37251d0e250
 2019-07-05 14:09:04 +03:00
Michel Heily 058760d7e4 Impl thumb Format4 
Former-commit-id: 7b8705ee7b76bbeb5b2a21e830d16db06ce8d63c
 2019-07-05 13:58:26 +03:00
Michel Heily 01290f6a28 Impl Thumb LdrStrSp 
Untested.


Former-commit-id: 8fa842d4969e30247fc1706dfe053c7dfbb37843
 2019-07-05 13:20:37 +03:00
Michel Heily be9499c76d Move cycle counting to CPU Core 
This isn't accurate, I'm probably missing something but at least it'll
make the instruction implementation more clean for now..


Former-commit-id: de24b15e1a51e1998207e5ea96fc8543f2553a26
 2019-07-05 13:08:07 +03:00
Michel Heily f8ebe26e5e Implement thumb format 13 
(NOT TESTED)


Former-commit-id: 160ee3a6c09a12cab53f69c94b385ea17666bd5f
 2019-07-05 03:46:04 +03:00
Michel Heily 5df9b6f317 Add thumb push-pop. 
Not tested, cycle modeling is crap


Former-commit-id: a5092dab79a1a660fc6c96a71f0908cc2054be27
 2019-07-05 03:28:02 +03:00
Michel Heily e66a8a9a3b Fix LR again :( 
Former-commit-id: 820315154ae58dcc29c4a8921094598f149b0255
 2019-07-05 03:27:23 +03:00
Michel Heily 2293300260 Add test for the bug fixed on e2a1303 
Former-commit-id: 98d0789aaf92a549cbe1b387461fd9acd4d773c0
 2019-07-04 02:06:41 +03:00
Michel Heily 702a08e30c Add many thumb instructions.. 
TODO add more tests for all the instructions I've got implemented so
far.
Also, I need to rewrite the whole "sysbus" module again because it's
crap and I keep refactoring it as I go.
I've added the "Dummy" because the bios for some reason tries to memzero
an unmapped region on the work ram (the thumb loop that ends at 0x126)


Former-commit-id: 67befd0935ee10df9ac8ceeaebd14f69767a7f16
 2019-07-04 01:56:50 +03:00
Michel Heily 984b17fa39 Fix arm mode STR insn 
Former-commit-id: 80903a9054e9b0dac07a5e2bb3cff7b0e722d438
 2019-07-04 01:56:11 +03:00
Michel Heily 923032f8cf REPL UI changes 
Former-commit-id: 6852b86541f967785dbffb6833fc2c11fa5dbef3
 2019-07-04 01:37:47 +03:00
Michel Heily 3541779fbf Fix LR when changing cpu modes 
Former-commit-id: 0ac911ee90758b9bffaafd459f1d9bca86d5064d
 2019-07-04 01:37:05 +03:00
= 28743702a1 Update waitstates for 256k work ram 
Former-commit-id: f5680c90e4ab4a9b29899cd5e0fe316d8227fc24
 2019-07-03 11:30:00 +03:00
Michel Heily eaf972de93 Implement thumb format 6 (PC-Relative Load) and test it. 
Former-commit-id: ae161edb0c8968913d2ef72a14053c118c6f7692
 2019-07-03 02:15:16 +03:00
Michel Heily 58e1230e7a Model the cartidge. 
Former-commit-id: b51d2928631bfc438b9f1b15fafcaa9d90008179
 2019-07-03 01:40:08 +03:00
Michel Heily b82874809f Implement thumb format3 instruction and add a test for it. 
Former-commit-id: 8cf6664027dc3d5dbeb6d2ca3d089820baac2709
 2019-07-03 01:26:48 +03:00
Michel Heily 4011911cca Pass around "Bus" instead of "SysBus" 
Former-commit-id: c20dae7dd3ddcb3bd8f671a16fd67a241bd6c459
 2019-07-03 01:22:36 +03:00
Michel Heily 6f81c236a6 Mega Commit #2 - Add some thumb decoding and disassembly 
Former-commit-id: e3a89ac681a8d6f6f0bee85b32f64d181e11242f
 2019-07-03 00:03:35 +03:00
Michel Heily cbddeffd91 arm: Implement MSR_REG and fix some prefetching errors 
Former-commit-id: 177b8966159ed86472b0d4d031363df72d46807a
 2019-07-02 16:53:29 +03:00
Michel Heily 05fb40c17c debugger: Add Deref expression. 
i.e:
r5 = *r6
r5 = *(u8*)r6
r5 = *(u16*)0x08000000


Former-commit-id: 962dade8e3c0b9f291115285137cf51b0abde266
 2019-07-02 13:36:52 +03:00
Michel Heily 645e71ac40 Remove garbage file 
Former-commit-id: 906b8bc6f6b95ddc3565043ff4406a403e7ba08a
 2019-07-01 19:26:52 +03:00
Michel Heily 70179984d0 cpu: arm: Fix alu_add_update_carry function 
Woopsie


Former-commit-id: 2da74e4bfd4b59a2885519a99f4b2c3d83031ee2
 2019-07-01 19:25:42 +03:00
Michel Heily 2081b70ee2 cpu: arm: Fix R14 for branch with link instruction 
Former-commit-id: bc927d86e5a170b0e4568b4ceeb7832d23ad309c
 2019-07-01 19:24:52 +03:00
Michel Heily ea8c4f2a60 Refactor ArmInstructionFormat => ArmFormat 
Former-commit-id: 0ba6e1e6efedad55b2716b3f2ab5a2a629dd18a5
 2019-07-01 17:51:07 +03:00
Michel Heily 6b225d776d Implement all memory mappings. Reformat many files. 
Former-commit-id: c0a62b610e62d2db2a4daf4aeef40068820daa52
 2019-07-01 17:45:29 +03:00
Michel Heily 22c175d9cc Reorganize package structure 
Former-commit-id: d7ad26c07fc7063522fae061577f7ceece797ae5
 2019-07-01 16:15:42 +03:00
Michel Heily bd053354cb Implement LDR/STR (not tested) and add cycle counting 
Former-commit-id: ec9e6bfc2a94291e47d41ff7d839007879d3d694
 2019-06-30 16:59:37 +03:00
Michel Heily 98eee121fc Correct F flag behaviour when entrying an exception. 
Former-commit-id: b0ef6352d9f0c027657c6e5eeb615a131e9523d2
 2019-06-29 23:01:23 +03:00
Michel Heily 967ccca8dd Mega commit - model CPU pipelining. 
I except many bugs to arise..


Former-commit-id: bcc6ea57af803f783b0dd548b50956b3ccda2b1a
 2019-06-29 22:23:12 +03:00
Michel Heily 4c75970512 debugger: Detect error 
Former-commit-id: 1ea605eeab1a7b8e6645fe11d7b32c4c7dff0750
 2019-06-29 01:48:29 +03:00
Michel Heily c90448075f debugger: Fix breakpoint hit message 2019-06-28 15:07:29 +03:00
Michel Heily 3429b67c41 Fix test_decode_branch_backwards failing 2019-06-28 13:09:30 +03:00
Michel Heily bd7fd472cf arm: Add tests for ldr/str 
And also test disassembling while at it..
 2019-06-28 12:36:19 +03:00
Michel Heily 7898bf61f3 arm: Fix bug when calculating 24bit branch offsets, and add a test for 
it.
 2019-06-28 12:01:49 +03:00
Michel Heily d11620e65b cpu: Add SWI instruction 
Also cleanup code, and add a test for swi decoding
 2019-06-28 11:46:36 +03:00
Michel Heily 1a0725f1a3 cpu: Model exceptions 2019-06-27 15:13:38 +03:00
Michel Heily fc6410b510 debugger: Make prompt bold 2019-06-27 15:04:15 +03:00
Michel Heily 1d766e95de cpu: Fix bug in psr mode bits 2019-06-27 15:03:44 +03:00
Michel Heily b9d1d38c2d debugger: Few improvements 2019-06-27 13:16:00 +03:00
Michel Heily 6552329310 cpu: Kinda implement data processing instructions 
When I say "Kinda", I mean that it is not tested well.
 2019-06-27 13:16:00 +03:00
Michel Heily 5808c03fcd cpu: Model Program Status Register. 2019-06-27 13:15:46 +03:00
Michel Heily 8a057ba159 debugger: Remember last command 2019-06-27 13:15:46 +03:00
Michel Heily 587ec3fc91 debugger: Add history to repl 2019-06-27 13:15:46 +03:00
Michel Heily f45a856835 Support assignment expressions for registers! 2019-06-27 13:15:46 +03:00
Michel Heily f1f33d8586 Improve debugger repl parsing. 
Add assignment expressions, add tests, and cleanup code.
 2019-06-27 13:15:46 +03:00
Michel Heily a70b92d5a4 Rename project 2019-06-27 13:15:46 +03:00
Michel Heily fc400ace5f Improve debug repl parsing :) 2019-06-27 13:15:46 +03:00
Michel Heily e5d93f689f Work.. 
Refactor disassembler to a struct.
Implement more commands;
 2019-06-27 13:15:34 +03:00
Michel Heily 22a915ec85 Add continue command 2019-06-27 13:15:34 +03:00
Michel Heily 9921f1c974 Add info and reset commands 2019-06-27 13:15:34 +03:00
Michel Heily fc28d89097 Implement a few debugger commands 2019-06-27 13:15:34 +03:00
Michel Heily 107e34aca1 Start debugger repl 2019-06-27 13:15:34 +03:00
Michel Heily 9330c53957 Start modeling CPU 
Wrote a shallow skeleton of a CPU Core.
Finally made the disassembler a clap subcommand.
 2019-06-27 13:15:19 +03:00
Michel Heily addea1efa0 Merge both packages 2019-06-24 22:02:00 +03:00
Michel Heily 094cbb5f29 Refactor disassembler binary into arm7tdmi package 2019-06-24 21:45:25 +03:00
Michel Heily 5a5efae4c0 Refactor disassembler => disass 2019-06-24 20:53:56 +03:00
Michel Heily dffb739d47 Finish disassembler for now 2019-06-24 20:20:08 +03:00